Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance

This paper investigates the circuit performance improvement through poly-pitch scaling in strain engineered devices. We use tensile contact etch stop liner(t-CESL), compressive contact etch stop liner(c-CESL), embedded SiC and SiGe as stress sources in NMOS and PMOS devices. It is observed that poly-pitch optimization delivers ~18% and ~13% reduction in delay of an inverter driving FO4 and FOl loads respectively. We observe that, in the presence of process induced mechanical stress; the optimum poly-pitch depends upon the size of the driver and the load. Finally, we present a model for choosing optimum poly-pitch for enhanced circuit performance while taking care of the power constraint.

[1]  Scott E. Thompson,et al.  Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs , 2009 .

[2]  Marco Zorzi,et al.  Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs , 2010, 2010 International Conference on Simulation of Semiconductor Processes and Devices.

[3]  H. Tsuno,et al.  Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation , 2007, 2007 IEEE Symposium on VLSI Technology.

[4]  E. Simoen,et al.  Gate Influence on the Layout Sensitivity of $ \hbox{Si}_{1 - x}\hbox{Ge}_{x}\ \hbox{S/D}$ and $\hbox{Si}_{1 - y}\hbox{C}_{y}\ \hbox{S/D}$ Transistors Including an Analytical Model , 2008, IEEE Transactions on Electron Devices.

[5]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[6]  S. Thompson,et al.  Future of Strained Si/Semiconductors in Nanoscale MOSFETs , 2006, 2006 International Electron Devices Meeting.

[7]  David Z. Pan,et al.  Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Ming Cai,et al.  Advanced strain engineering for state-of-the-art nanoscale CMOS technology , 2011, Science China Information Sciences.

[9]  V. Moroz,et al.  pMOSFET with 200% mobility enhancement induced by multiple stressors , 2006, IEEE Electron Device Letters.

[10]  Yu Tian,et al.  Challenges of 22 nm and beyond CMOS technology , 2009, Science in China Series F: Information Sciences.

[11]  Jun Luo,et al.  Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status , 2011 .

[12]  Manfred Horstmann,et al.  Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors , 2010 .

[13]  S. Narasimha,et al.  Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current , 2007, 2007 IEEE Symposium on VLSI Technology.

[14]  Ming-Shing Chen,et al.  Effect of Finger Pitch on the Driving Ability of a 40-nm MOSFET With Contact Etch Stop Layer Strain in Multifinger Gated Structure , 2010, IEEE Transactions on Electron Devices.

[15]  G. Eneman,et al.  Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study , 2007, IEEE Transactions on Electron Devices.

[16]  E.J. Nowak,et al.  The effective drive current in CMOS inverters , 2002, Digest. International Electron Devices Meeting,.