Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

[1]  B. Parvais,et al.  Stochastic Matching Properties of FinFETs , 2006, IEEE Electron Device Letters.

[2]  G. Dewey,et al.  Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[3]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[4]  R. Rooyackers,et al.  A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[5]  Paul Zimmerman,et al.  Tall triple-gate device with TiN/HfO2 gate stack , 2005 .

[6]  R. Rooyackers,et al.  Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[7]  E. Sleeckx,et al.  Performance improvement of tall triple gate devices with strained SiN layers , 2005, IEEE Electron Device Letters.

[8]  N. Collaert,et al.  Analysis of the parasitic S/D resistance in multiple-gate FETs , 2005, IEEE Transactions on Electron Devices.

[9]  Chi On Chui,et al.  Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[10]  P. Wambacq,et al.  Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[11]  R. Rooyackers,et al.  Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[12]  Vincent Wiaux,et al.  Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits , 2005 .

[13]  R. Rooyackers,et al.  A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM , 2007, 2007 IEEE Symposium on VLSI Technology.

[14]  Jong-Tea Park,et al.  Pi-Gate SOI MOSFET , 2001, IEEE Electron Device Letters.

[15]  Tsu-Jae King,et al.  Improvement of FinFET electrical characteristics by hydrogen annealing , 2004, IEEE Electron Device Letters.

[16]  Rita Rooyackers,et al.  Comprehensive approach to MuGFET metrology , 2006, SPIE Advanced Lithography.

[17]  Vincent Wiaux,et al.  Challenges in patterning 45nm node multiple-gate devices and SRAM cells , 2004 .

[18]  A. Hikavyy,et al.  Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography , 2007, 2007 IEEE Symposium on VLSI Technology.

[19]  G. Pei,et al.  FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .

[20]  R. Rooyackers,et al.  Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency , 2006, 2006 International Electron Devices Meeting.