论文信息 - Circuit implementation of piecewise-affine functions based on a binary search tree

Circuit implementation of piecewise-affine functions based on a binary search tree

In this paper we introduce a digital architecture implementing piecewise-affine functions defined over domains partitioned into polytopes: the functions are linear affine over each polytope. The polytope containing the input vector is found by exploring a previously constructed binary search tree. Once the polytope is detected, the function is evaluated by addressing an affine map whose coefficients are stored in a memory. The architecture has been implemented on FPGA and experimental results for a benchmark example are shown.

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