Fast scientific computation in CMOS VLSI shared-memory multiprocessors

The authors present design considerations for fast and efficient scientific computation in CMOS VLSI in general, and shared memory multiprocessors in particular, using SPUR as a case study. Algorithmic and technological tradeoffs for fast floating-point arithmetic are presented, together with design issues in tightly-coupled coprocessor interfaces. SPUR simulations indicate that basic arithmetic operations are three to ten times faster than current single-chip VLSI floating-point coprocessors, and communication overhead between CPU and FPU in a single-node system is five to ten times less than commercial microprocessor-based systems. System speed-up and potential bottlenecks with shared-memory multiprocessors are presented.<<ETX>>

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