A 6b 46GS/s ADC with >23GHz BW and sparkle-code error correction

This paper presents a 6b 46GS/s 72-way hierarchically time-interleaved asynchronous SAR ADC utilizing cascode samplers to achieve >23GHz BW. A back-end meta-stability correction circuit enables sparkle-code error-free operation over 1e10 samples. The 28nm FDSOI ADC achieves 27dB SNDR (low frequency)/25.2dB (at 23.5GHz) while consuming 381mW from 1.05V/1.6V supplies and occupies 0.14mm2.

[1]  Sang-Gug Lee,et al.  A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Ian Dedic.  56Gs/s ADC : Enabling 100GbE , 2010, 2010 Conference on Optical Fiber Communication (OFC/NFOEC), collocated National Fiber Optic Engineers Conference.

[3]  Boris Murmann,et al.  A/D converter circuit and architecture design for high-speed data communication , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.