Analysis of voltage scaling effects in the design of resilient circuits

Embora o avanco da tecnologia de semicondutores permita a fabricacao de dispositivos com atrasos de propagacao reduzidos, potencialmente habilitando o aumento da frequencia de operacao, as variacoes em processos de fabricacao modernos crescem de forma muito agressiva. Para lidar com este problema, significativas margens de atraso devem ser adicionadas ao periodo de sinais de relogio, limitando os ganhos em desempenho e a eficiencia energetica do circuito. Entre as diversas tecnicas exploradas nas ultimas decadas para amenizar esta dificuldade, tres se destacam como relevantes e promissoras, isoladas ou combinadas: a reducao da tensao de alimentacao, o uso de projeto assincrono e arquiteturas resilientes. Este trabalho investiga como a reducao de tensao de alimentacao afeta os atrasos de caminhos em circuitos digitais, e produz tres contribuicoes originais. A primeira e a definicao uma tecnica para garantir que circuitos sintetizados com um conjunto reduzido de celulas atinjam resultados comparaveis aos da biblioteca completa, mantendo a sua funcionalidade mesmo quando alimentados por tensoes reduzidas. A segunda e a composicao de um metodo para estender o suporte a niveis de tensao de alimentacao para bibliotecas de celulas padrao providas por fabicantes de CIs, atraves de novas tecnicas de caracterizacao de bibliotecas. A terceira e a analise dos efeitos do escalamento de tensao no projeto de circuitos resilientes, considerando tensoes de alimentacao superiores e inferiores a tensao de limiar dos transistores.

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