Enhancement strategies for multistage interconnection networks

Multistage interconnection networks (MINs) are widely used as a communication mechanism in multiprocessor systems because they possess several important characteristics. The main advantage of MINs is their modularity which eases their implementation. However, the main limitations of MINs are scalability and latency. This work presents two approaches to overcome these limitations by employing a general approach and an application specific scheme. The general approach combines the features of both hierarchical networks and MINs in the form of a new topology called Hierarchical Multistage Interconnection Network (HMIN). The HMIN architecture is evaluated for its performance and it is shown that it out performs MINs under most conditions and always better cost-effectiveness than MINs. HMIMs are also shown to be more suitable architectures from a VLSI implementation perspective. The second approach consists of analysis and design algorithms for MINs. Analysis algorithms are developed which present the tightest upper and lower bounds on the number of passes required to realize a permutation on a MIN (determining the exact number is known to be NP-Complete). Two design algorithms are developed--one results in a MIN belonging to the Shuffle-Exchange class and the other results in a MIN belonging to a general Biped class of networks.