Intractability in linear switch-level simulation

The linear switch-level model represents a MOS transistor as a voltage-controlled linear resistor and a storage node as a grounded, linear capacitor. For logic simulation, the linear switch-level model offers an attractive tradeoff between resolution/accuracy and computational complexity over gate-level and circuit-level models. However, analysis of MOS networks using the linear switch-level model becomes increasingly difficult in the presence of unknown values, and heuristic methods are often employed. It is shown that the complexity of computing maximum and minimum steady-state voltages of a general MOS network using the linear switch-level model in the presence of unknown values is NP-complete. These results partially justify the use of heuristic methods when unknown values are present. >

[1]  R. A. Rohrer.  Circuit partitioning simplified , 1988 .

[2]  John K. Ousterhout.  Switch-Level Delay Models for Digital MOS VLSI , 1984, 21st Design Automation Conference Proceedings.

[3]  R. Rohrer.  The Generalized Adjoint Network and Network Sensitivities , 1969 .

[4]  Randal E. Bryant.  A SWITCH-LEVEL SIMULATION MODEL FOR INTEGRATED LOGIC CIRCUITS , 1981 .

[5]  N. C. Rumin,et al.  Magnitude classes in switch-level modeling , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[6]  Randal E. Bryant,et al.  A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.

[7]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Randal E. Bryant,et al.  Boolean Analysis of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Daniel P. Lopresti,et al.  Modeling uncertainty in RC timing analysis , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Randal E. Bryant,et al.  Algorithmic Aspects of Symbolic Switch Network Analysis , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  John K. Ousterhout.  Crystal: a Timing Analyzer for nMOS VLSI Circuits , 1983 .

[12]  Paul Penfield,et al.  Signal Delay in RC Tree Networks , 1981, 18th Design Automation Conference.