A new error masking flip-flop with one cycle correction penalty

The dynamic timing variation under the nanometer CMOS technology becomes a major problem for IC design. A typical way to eliminate the timing margin for variation is using on-line timing Error Detection and Correction (EDC) technique. However, most of EDC techniques require a large amount of transistor count and result in area overhead. To address this issue, a new Error Masking Flip-Flop (EMFF) is proposed. Compared with other previous error resilience cells, the proposed EMFF achieves self-correction with the least transistor counts. To study the benefits of EMFF, a 3-stages embedded CPU is implemented in 40-nm CMOS technology. According to the experimental results, design with EMFF can tolerate frequency and voltage variations. Moreover, compared with margined baseline, design with EMFF achieves 3.3× performance and 1.6× energy-efficiency at 0.9 V supply voltage.