On-Chip Networks, Second Edition

Abstract This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short sy...

[1]  Amit Kumar,et al.  NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[2]  Babak Falsafi,et al.  NOC-Out: Microarchitecting a Scale-Out Processor , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[3]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[4]  Chen Sun,et al.  A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning , 2016, IEEE Journal of Solid-State Circuits.

[5]  Natalie D. Enright Jerger,et al.  Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[6]  Antonia Zhai,et al.  Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems , 2014, 2014 IEEE 28th International Parallel and Distributed Processing Symposium.

[7]  Partha Pratim Pande,et al.  Testing Network-on-Chip Communication Fabrics , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Yong Liu,et al.  A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[9]  William J. Dally,et al.  A Delay Model for Router Microarchitectures , 2001, IEEE Micro.

[10]  Milos Prvulovic,et al.  TLSync: Support for multiple fast barriers using on-chip transmission lines , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[11]  Kees G. W. Goossens,et al.  Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Rami G. Melhem,et al.  Déjà Vu Switching for Multiplane NoCs , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[13]  Partha Pratim Pande,et al.  Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[14]  Mark D. Hill,et al.  Virtual hierarchies to support server consolidation , 2007, ISCA '07.

[15]  Kunle Olukotun,et al.  The case for a single-chip multiprocessor , 1996, ASPLOS VII.

[16]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[17]  Doug Burger,et al.  Implementation and Evaluation of On-Chip Network Architectures , 2006, 2006 International Conference on Computer Design.

[18]  Bevan M. Baas,et al.  A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Fabrizio Petrini,et al.  Cell Multiprocessor Communication Network: Built for Speed , 2006, IEEE Micro.

[20]  David Blaauw,et al.  Vicis: A reliable network for unreliable silicon , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[21]  Mikko H. Lipasti,et al.  Circuit-Switched Coherence , 2008 .

[22]  Tianshi Chen,et al.  ShiDianNao: Shifting vision processing closer to the sensor , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[23]  Natalie D. Enright Jerger,et al.  Improving DVFS in NoCs with Coherence Prediction , 2015, NOCS.

[24]  Natalie D. Enright Jerger,et al.  Dodec: Random-Link, Low-Radix On-Chip Networks , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[25]  Luca P. Carloni,et al.  On the Design of a Photonic Network-on-Chip , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[26]  Alain Greiner,et al.  SPIN: a scalable, packet switched, on-chip micro-network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[27]  OpenSoC Fabric: On-chip network generator , 2016, 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[28]  Ajaykumar Kannan,et al.  Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors , 2016, IEEE Micro.

[29]  David Blaauw,et al.  Scaling towards kilo-core processors with asymmetric high-radix topologies , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[30]  Michal Lipson,et al.  WDM-compatible mode-division multiplexing on a silicon chip , 2014, Nature Communications.

[31]  Norman P. Jouppi.  System implications of integrated photonics , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[32]  William J. Dally,et al.  Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels , 1993, IEEE Trans. Parallel Distributed Syst..

[33]  Niraj K. Jha,et al.  In-Network Coherence Filtering: Snoopy coherence without broadcasts , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[34]  John Kim,et al.  Throughput-Effective On-Chip Networks for Manycore Accelerators , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[35]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[36]  José Duato,et al.  An Efficient Implementation of Distributed Routing Algorithms for NoCs , 2008 .

[37]  Mikko H. Lipasti,et al.  Wavelength stealing: An opportunistic approach to channel sharing in multi-chip photonic interconnects , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[38]  Lizhong Chen,et al.  Bubble coloring: avoiding routing- and protocol-induced deadlocks with minimal virtual channel requirement , 2013, ICS '13.

[39]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[40]  Hoi-Jun Yoo,et al.  A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition , 2010, IEEE Journal of Solid-State Circuits.

[41]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[42]  Vaughn Betz,et al.  Design tradeoffs for hard and soft FPGA-based Networks-on-Chip , 2012, 2012 International Conference on Field-Programmable Technology.

[43]  Timothy Mark Pinkston,et al.  Characterization of Deadlocks in k-ary n-Cube Networks , 1999, IEEE Trans. Parallel Distributed Syst..

[44]  Vincenzo Catania,et al.  A methodology for design of application specific deadlock-free routing algorithms for NoC systems , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[45]  José Duato,et al.  Deadlock-free dynamic reconfiguration over InfiniBand™ NETWORKS , 2004, Parallel Algorithms Appl..

[46]  Natalie D. Enright Jerger,et al.  Supporting efficient collective communication in NoCs , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[47]  Radu Marculescu,et al.  An Analytical Approach for Network-on-Chip Performance Analysis , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[48]  Fabien Clermidy,et al.  An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[49]  Zhiping Zhou,et al.  On-chip light sources for silicon photonics , 2015, Light: Science & Applications.

[50]  Yu Zhang,et al.  Firefly: illuminating future network-on-chip with nanophotonics , 2009, ISCA '09.

[51]  Yu Hen Hu,et al.  BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[52]  Natalie D. Enright Jerger,et al.  NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free? , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[53]  Avinash Sodani,et al.  Knights landing (KNL): 2nd Generation Intel® Xeon Phi processor , 2015, 2015 IEEE Hot Chips 27 Symposium (HCS).

[54]  Massoud Pedram,et al.  Power punch: Towards non-blocking power-gating of NoC routers , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[55]  Sudhakar Yalamanchili,et al.  Bubble sharing: Area and energy efficient adaptive routers using centralized buffers , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[56]  Balaram Sinharoy,et al.  POWER4 system microarchitecture , 2002, IBM J. Res. Dev..

[57]  Timothy Mattson,et al.  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[58]  Massoud Pedram,et al.  Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator , 2016, J. Parallel Distributed Comput..

[59]  Natalie D. Enright Jerger,et al.  Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[60]  Jörg Henkel,et al.  On-chip networks: a scalable, communication-centric embedded system design paradigm , 2004, 17th International Conference on VLSI Design. Proceedings..

[61]  Henry Wong,et al.  Analyzing CUDA workloads using a detailed GPU simulator , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[62]  James C. Hoe,et al.  CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs , 2012, FPGA '12.

[63]  Niraj K. Jha,et al.  GARNET: A detailed on-chip network model inside a full-system simulator , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

[64]  Chita R. Das,et al.  A novel dimensionally-decomposed router for on-chip communication in 3D architectures , 2007, ISCA '07.

[65]  Hsien-Hsin S. Lee,et al.  3D-MAPS: 3D Massively parallel processor with stacked memory , 2012, 2012 IEEE International Solid-State Circuits Conference.

[66]  Xi Chen,et al.  Dynamic voltage and frequency scaling for shared resources in multicore processor designs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[67]  Shubhendu S. Mukherjee,et al.  The Alpha 21364 Network Architecture , 2002, IEEE Micro.

[68]  Jie Wu,et al.  Latency criticality aware on-chip communication , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[69]  Radu Marculescu,et al.  Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[70]  Ray T. Chen,et al.  O-Router: An optical routing framework for low power on-chip silicon nano-photonic integration , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[71]  Chita R. Das,et al.  ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[72]  George Kurian,et al.  ATAC: A 1000-core cache-coherent processor with on-chip optical network , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[73]  Cruz Izu,et al.  The Adaptive Bubble Router , 2001, J. Parallel Distributed Comput..

[74]  Steve Scott,et al.  The Cray BlackWidow: a highly scalable vector multiprocessor , 2007, Proceedings of the 2007 ACM/IEEE Conference on Supercomputing (SC '07).

[75]  Rajeev J. Ram,et al.  Single-chip microprocessor that communicates directly using light , 2015, Nature.

[76]  William J. Dally,et al.  A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[77]  A. Jose,et al.  Near speed-of-light on-chip interconnects using pulsed current-mode signalling , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[78]  Kees G. W. Goossens,et al.  Congestion-Controlled Best-Effort Communication for Networks-on-Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[79]  Luca Benini,et al.  ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip , 2004, DATE.

[80]  Timothy Mark Pinkston,et al.  A methodology for designing efficient on-chip interconnects on well-behaved communication patterns , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[81]  Hideharu Amano,et al.  A Lightweight Fault-Tolerant Mechanism for Network-on-Chip , 2008 .

[82]  Li-Shiuan Peh,et al.  Enabling system-level modeling of variation-induced faults in Networks-on-Chips , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[83]  D.A.B. Miller,et al.  Rationale and challenges for optical interconnects to electronic chips , 2000, Proceedings of the IEEE.

[84]  Hoi-Jun Yoo,et al.  Low-power network-on-chip for high-performance SoC design , 2006, IEEE Trans. Very Large Scale Integr. Syst..

[85]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[86]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[87]  Xiaomin Zhang,et al.  Characterization & analysis of a server consolidation benchmark , 2008, VEE '08.

[88]  John Kim,et al.  Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[89]  Vivienne Sze,et al.  14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks , 2016, ISSCC.

[90]  Chita R. Das,et al.  Application-aware prioritization mechanisms for on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[91]  Saurabh Dighe,et al.  A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.

[92]  Scott A. Mahlke,et al.  BulletProof: a defect-tolerant CMP switch architecture , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[93]  Cheng Li,et al.  A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization , 2016, IEEE Journal of Solid-State Circuits.

[94]  Ulf Schlichtmann,et al.  PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip , 2016, ISPD.

[95]  James Demmel,et al.  the Parallel Computing Landscape , 2022 .

[96]  Mauricio Hanzich,et al.  Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach , 2015, IEEE Micro.

[97]  José Luis Martín,et al.  Overview of FPGA-Based Multiprocessor Systems , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[98]  Leonard Kleinrock,et al.  Virtual Cut-Through: A New Computer Communication Switching Technique , 1979, Comput. Networks.

[99]  Gerard J. M. Smit,et al.  An energy-efficient reconfigurable circuit-switched network-on-chip , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[100]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[101]  D. Lenoski,et al.  The SGI Origin: A ccnuma Highly Scalable Server , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[102]  Natalie D. Enright Jerger,et al.  DART: A Programmable Architecture for NoC Simulation on FPGAs , 2014, IEEE Trans. Computers.

[103]  Erik Lindholm,et al.  NVIDIA Tesla: A Unified Graphics and Computing Architecture , 2008, IEEE Micro.

[104]  Srinivas Devadas,et al.  Oblivious Routing in On-Chip Bandwidth-Adaptive Networks , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.

[105]  Josep Torrellas,et al.  WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication , 2016, ASPLOS.

[106]  Timothy Mark Pinkston,et al.  A design methodology for efficient application-specific on-chip interconnects , 2006, IEEE Transactions on Parallel and Distributed Systems.

[107]  Jason Cong,et al.  CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[108]  Hoi-Jun Yoo,et al.  A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[109]  Steve Blair,et al.  Crossing-Aware Channel Routing for Integrated Optics , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[110]  Chung-Ta King,et al.  TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[111]  Jason Cong,et al.  Power reduction of CMP communication networks via RF-interconnects , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[112]  David H. Albonesi,et al.  Phastlane: a rapid transit optical routing network , 2009, ISCA '09.

[113]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[114]  Li Shang,et al.  In-Network Cache Coherence , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[115]  Lizhong Chen,et al.  Worm-Bubble Flow Control , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[116]  Vaughn Betz,et al.  Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[117]  A. Kumary,et al.  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007 .

[118]  Luca P. Carloni,et al.  VANDAL: A tool for the design specification of nanophotonic networks , 2011, 2011 Design, Automation & Test in Europe.

[119]  Anant Agarwal,et al.  Anatomy of a message in the Alewife multiprocessor , 1993 .

[120]  Chita R. Das,et al.  A case for dynamic frequency tuning in on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[121]  George L.-T. Chiu,et al.  Overview of the Blue Gene/L system architecture , 2005, IBM J. Res. Dev..

[122]  Alyssa B. Apsel,et al.  Leveraging Optical Technology in Future Bus-based Chip Multiprocessors , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[123]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[124]  Ahmed Louri,et al.  QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[125]  Eduardo de la Torre,et al.  A Fast Emulation-Based NoC Prototyping Framework , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[126]  Axel Jantsch,et al.  Load distribution with the proximity congestion awareness in a network on chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[127]  Lizhong Chen,et al.  NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[128]  Natalie D. Enright Jerger,et al.  Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs , 2015, IEEE Transactions on Computers.

[129]  Daisuke Sasaki,et al.  3D NoC with Inductive-Coupling Links for Building-Block SiPs , 2014, IEEE Transactions on Computers.

[130]  Hui Wu,et al.  A case for globally shared-medium on-chip interconnect , 2011, ISCA.

[131]  Kevin Skadron,et al.  Rodinia: A benchmark suite for heterogeneous computing , 2009, 2009 IEEE International Symposium on Workload Characterization (IISWC).

[132]  Rishiyur S. Nikhil,et al.  Bluespec System Verilog: efficient, correct RTL from high level specifications , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..

[133]  G. Edward Suh,et al.  Static virtual channel allocation in oblivious routing , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[134]  Nachiket Kapre,et al.  Hoplite: Building austere overlay NoCs for FPGAs , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[135]  Valentin Puente,et al.  Rotary router: an efficient architecture for CMP interconnection networks , 2007, ISCA '07.

[136]  Krishnan Srinivasan,et al.  A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[137]  Vaughn Betz,et al.  Take the Highway: Design for Embedded NoCs on FPGAs , 2015, FPGA.

[138]  John Kim,et al.  FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[139]  Ren Wang,et al.  Energy-efficient interconnect via Router Parking , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[140]  Natalie D. Enright Jerger,et al.  Efficient synthetic traffic models for large, complex SoCs , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[141]  Valeria Bertacco,et al.  Brisk and limited-impact NoC routing reconfiguration , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[142]  Sharad Malik,et al.  Power-driven design of router microarchitectures in on-chip networks , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[143]  Natalie D. Enright Jerger,et al.  DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[144]  José Duato,et al.  Efficient unicast and multicast support for CMPs , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[145]  Lizhong Chen,et al.  MP3: Minimizing performance penalty for power-gating of Clos network-on-chip , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[146]  Hsien-Hsin S. Lee,et al.  Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) , 2015, IEEE Transactions on Computers.

[147]  Natalie D. Enright Jerger,et al.  DART: A Programmable Architecture for NoC Simulation on FPGAs , 2014, IEEE Transactions on Computers.

[148]  Hyungjun Kim,et al.  Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[149]  Anantha Chandrakasan,et al.  Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI , 2012, DAC Design Automation Conference 2012.

[150]  Huawei Li,et al.  An abacus turn model for time/space-efficient reconfigurable routing , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[151]  S. Lennart Johnsson,et al.  ROMM routing on mesh and torus networks , 1995, SPAA '95.

[152]  H. Peter Hofstee,et al.  Introduction to the Cell multiprocessor , 2005, IBM J. Res. Dev..

[153]  Idit Keidar,et al.  NoC-Based FPGA: Architecture and Routing , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[154]  David Blaauw,et al.  High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[155]  William J. Dally,et al.  The J-machine network , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[156]  Ki Hwan Yum,et al.  APCR: An adaptive physical channel regulator for On-Chip Interconnects , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

[157]  Paolo Giaccone,et al.  Rate-based vs delay-based control for DVFS in NoC , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[158]  Hideharu Amano,et al.  Prediction router: Yet another low latency on-chip router architecture , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[159]  Venkatesh Akella,et al.  Inferring packet dependencies to improve trace based simulation of on-chip networks , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[160]  Kunle Olukotun,et al.  Niagara: a 32-way multithreaded Sparc processor , 2005, IEEE Micro.

[161]  T. N. Vijaykumar,et al.  Adaptive Flow Control for Robust Performance and Energy , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[162]  Xi Chen,et al.  Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[163]  Radu Marculescu,et al.  Dynamic power management for multidomain system-on-chip platforms , 2013, ACM Trans. Design Autom. Electr. Syst..

[164]  John Kim,et al.  Low-cost router microarchitecture for on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[165]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[166]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[167]  David R. Kaeli,et al.  Leveraging Silicon-Photonic NoC for Designing Scalable GPUs , 2015, ICS.

[168]  Nan Jiang,et al.  A detailed and flexible cycle-accurate Network-on-Chip simulator , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[169]  John Wawrzynek,et al.  Chisel: Constructing hardware in a Scala embedded language , 2012, DAC Design Automation Conference 2012.

[170]  Karthik Ramani,et al.  Leveraging Wire Properties at the Microarchitecture Level , 2006, IEEE Micro.

[171]  Saurabh Dighe,et al.  An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[172]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[173]  William J. Dally,et al.  Digital systems engineering , 1998 .

[174]  Yuan Yao,et al.  Memory-access aware DVFS for network-on-chip in CMPs , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[175]  Niraj K. Jha,et al.  Token flow control , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[176]  Onur Mutlu,et al.  Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[177]  Mahmut T. Kandemir,et al.  Addressing End-to-End Memory Access Latency in NoC-Based Multicores , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[178]  Steve Blair,et al.  Thermal-aware synthesis of integrated photonic ring resonators , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[179]  Nan Jiang,et al.  Packet chaining: Efficient single-cycle allocation for on-chip networks , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[180]  William J. Dally,et al.  Locality-preserving randomized oblivious routing on torus networks , 2002, SPAA '02.

[181]  Li-Shiuan Peh,et al.  ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment , 2011, 2011 International Conference on Parallel Architectures and Compilation Techniques.

[182]  Rudy Lauwereins,et al.  Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.

[183]  Giovanni De Micheli,et al.  A complete network-on-chip emulation framework , 2005, Design, Automation and Test in Europe.

[184]  David Blaauw,et al.  A highly resilient routing algorithm for fault-tolerant NoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[185]  Onur Mutlu,et al.  A case for bufferless routing in on-chip networks , 2009, ISCA '09.

[186]  M. Coppola,et al.  Spidergon: a novel on-chip communication network , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..

[187]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[188]  Axel Jantsch,et al.  Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[189]  Kenneth A. Ross,et al.  Q100: the architecture and design of a database processing unit , 2014, ASPLOS.

[190]  Bernard Brezzo,et al.  TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[191]  Vaughn Betz,et al.  The power of communication: Energy-efficient NOCS for FPGAS , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[192]  José Duato,et al.  A new theory of deadlock-free adaptive multicast routing in wormhole networks , 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

[193]  Jason Cong,et al.  Three Dimensional Integrated Circuit Design , 2010 .

[194]  Pat Conway,et al.  The AMD Opteron Northbridge Architecture , 2007, IEEE Micro.

[195]  David Blaauw,et al.  Swizzle-Switch Networks for Many-Core Systems , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[196]  Sudhakar Yalamanchili,et al.  Pipelined circuit-switching: a fault-tolerant variant of wormhole routing , 1992, [1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing.

[197]  Natalie D. Enright Jerger,et al.  An Evaluation of Server Consolidation Workloads for Multi-Core Designs , 2007, 2007 IEEE 10th International Symposium on Workload Characterization.

[198]  K. Goossens,et al.  rdwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[199]  Reetuparna Das,et al.  Application-to-core mapping policies to reduce memory system interference in multi-core systems , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[200]  Sudhakar Yalamanchili,et al.  Centralized buffer router: A low latency, low power router for high radix NOCs , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[201]  Rakesh Kumar,et al.  MOPED: Orchestrating interprocess message data on CMPs , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[202]  Lesley Shannon,et al.  The routability of multiprocessor network topologies in FPGAs , 2006, SLIP '06.

[203]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[204]  Marc Tremblay,et al.  A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[205]  Ran Ginosar,et al.  Routing Table Minimization for Irregular Mesh NoCs , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[206]  Yuval Tamir,et al.  Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches , 1992, IEEE Trans. Computers.

[207]  G. Edward Suh,et al.  Application-aware deadlock-free oblivious routing , 2009, ISCA '09.

[208]  David R. Kaeli,et al.  Asymmetric NoC Architectures for GPU Systems , 2015, NOCS.

[209]  William J. Dally,et al.  The message-driven processor: a multicomputer processing node with efficient mechanisms , 1992, IEEE Micro.

[210]  Jud Leonard,et al.  A Network Fabric for Scalable Multiprocessor Systems , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[211]  Radu Marculescu,et al.  "It's a small world after all": NoC performance optimization via long-range link insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[212]  James C. Hoe,et al.  CoRAM: an in-fabric memory architecture for FPGA-based computing , 2011, FPGA '11.

[213]  Stephen W. Keckler,et al.  Netrace: dependency-driven trace-based network-on-chip simulation , 2010, NoCArc '10.

[214]  Ulf Schlichtmann,et al.  PROTON: An automatic place-and-route tool for optical Networks-on-Chip , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[215]  Anantha Chandrakasan,et al.  40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[216]  Yuan Xie,et al.  LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[217]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[218]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[219]  Mark D. Hill,et al.  Coherence Ordering for Ring-based Chip Multiprocessors , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[220]  Mitchell Hayenga.  The NoX router , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[221]  Natalie D. Enright Jerger,et al.  Enabling interposer-based disintegration of multi-core processors , 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[222]  Marcello Coppola.  Spidergon STNoC: The technology that adds value to your System , 2010, 2010 IEEE Hot Chips 22 Symposium (HCS).

[223]  Alexander Sprintson,et al.  GCA: Global congestion awareness for load balance in Networks-on-Chip , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[224]  Jun Yang,et al.  A low-radix and low-diameter 3D interconnection network design , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[225]  Valeria Bertacco,et al.  uDIREC: Unified diagnosis and reconfiguration for frugal bypass of NoC faults , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[226]  Axel Jantsch,et al.  Methods for fault tolerance in networks-on-chip , 2013, CSUR.

[227]  Niraj K. Jha,et al.  Express virtual channels: towards the ideal interconnection fabric , 2007, ISCA '07.

[228]  Chita R. Das,et al.  Aérgia: exploiting packet latency slack in on-chip networks , 2010, ISCA.

[229]  Valeria Bertacco,et al.  Formally enhanced runtime verification to ensure NoC functional correctness , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[230]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[231]  John Shalf,et al.  Optical Interconnects and Extreme Computing , 2016 .

[232]  Doug Burger,et al.  An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches , 2002, ASPLOS X.

[233]  Radu Marculescu,et al.  Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs , 2016, IEEE Transactions on Computers.

[234]  Pedro López,et al.  Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[235]  William J. Dally,et al.  An Efficient, Protected Message Interface , 1998, Computer.

[236]  William J. Dally,et al.  The torus routing chip , 2005, Distributed Computing.

[237]  Timothy Mark Pinkston,et al.  A Formal Model of Message Blocking and Deadlock Resolution in Interconnection Networks , 2000, IEEE Trans. Parallel Distributed Syst..

[238]  Sri Parameswaran,et al.  NoCGEN:a template based reuse methodology for Networks On Chip architecture , 2004, 17th International Conference on VLSI Design. Proceedings..

[239]  George Michelogiannakis,et al.  Elastic-buffer flow control for on-chip networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[240]  Scott A. Mahlke,et al.  Reliable Systems on Unreliable Fabrics , 2008, IEEE Design & Test of Computers.

[241]  Natalie D. Enright Jerger,et al.  The runahead network-on-chip , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[242]  Valentin Puente,et al.  MRR: Enabling fully adaptive multicast routing for CMP interconnection networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[243]  Niraj K. Jha,et al.  In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[244]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[245]  Kiyoung Choi,et al.  A scalable processing-in-memory accelerator for parallel graph processing , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[246]  Radu Marculescu,et al.  System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[247]  Ashok V. Krishnamoorthy,et al.  Silicon-photonic network architectures for scalable, power-efficient multi-chip systems , 2010, ISCA '10.

[248]  Li-Shiuan Peh,et al.  Breaking the on-chip latency barrier using SMART , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[249]  Timothy Mark Pinkston,et al.  A Progressive Approach to Handling Message-Dependent Deadlock in Parallel Computer Systems , 2003, IEEE Trans. Parallel Distributed Syst..

[250]  Valentin Puente,et al.  TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[251]  Chen Sun,et al.  DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[252]  Tao Li,et al.  Exploring Silicon Nanophotonics in Throughput Architecture , 2014, IEEE Design & Test.

[253]  Muhammad Shafique,et al.  Malleable NoC: Dark silicon inspired adaptable Network-on-Chip , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[254]  David Wentzlaff,et al.  OpenPiton: An Open Source Manycore Research Framework , 2016, ASPLOS.

[255]  William J. Dally,et al.  The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers , 1994, PCRCW.

[256]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[257]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[258]  Eun Jung Kim,et al.  Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[259]  Natalie D. Enright Jerger,et al.  SCARAB: A single cycle adaptive routing and bufferless network , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[260]  Yuan Yao,et al.  DVFS for NoCs in CMPs: A thread voting approach , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[261]  Natalie D. Enright Jerger,et al.  Achieving predictable performance through better memory controller placement in many-core CMPs , 2009, ISCA '09.

[262]  Amin Ansari,et al.  Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[263]  Karthikeyan Sankaralingam,et al.  Implementation and Evaluation of a Dynamically Routed Processor Operand Network , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[264]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[265]  Li-Shiuan Peh,et al.  Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[266]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[267]  Chris Fallin,et al.  CHIPPER: A low-complexity bufferless deflection router , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[268]  Leslie G. Valiant,et al.  Universal schemes for parallel communication , 1981, STOC '81.

[269]  Luca Benini,et al.  MPARM: Exploring the Multi-Processor SoC Design Space with SystemC , 2005, J. VLSI Signal Process..

[270]  Jun Yang,et al.  Simple virtual channel allocation for high throughput and high frequency on-chip routers , 2010, HPCA.

[271]  Gerard J. M. Smit,et al.  Fast, Accurate and Detailed NoC Simulations , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[272]  Yuval Tamir,et al.  Symmetric Crossbar Arbiters for VLSI Communication Switches , 1993, IEEE Trans. Parallel Distributed Syst..

[273]  Giovanni De Micheli,et al.  An adaptive low-power transmission scheme for on-chip networks , 2002, 15th International Symposium on System Synthesis, 2002..

[274]  William J. Dally,et al.  Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks , 1989, IEEE Trans. Computers.

[275]  Jeffrey T. Draper,et al.  In-network traffic regulation for Transactional Memory , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[276]  Alberto L. Sangiovanni-Vincentelli,et al.  Efficient synthesis of networks on chip , 2003, Proceedings 21st International Conference on Computer Design.

[277]  Onur Mutlu,et al.  Preemptive Virtual Clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[278]  Li-Shiuan Peh,et al.  A low-swing crossbar and link generator for low-power networks-on-chip , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[279]  Chrysostomos Nicopoulos,et al.  NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[280]  Onur Mutlu,et al.  Express Cube Topologies for on-Chip Interconnects , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[281]  William J. Dally,et al.  Flit-reservation flow control , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[282]  Natalie D. Enright Jerger,et al.  Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[283]  Michael Burrows,et al.  Autonet: A High-Speed, Self-Configuring Local Area Network Using Point-to-Point Links , 1991, IEEE J. Sel. Areas Commun..

[284]  Sebastian Turullols,et al.  SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets , 2012, 2012 IEEE Hot Chips 24 Symposium (HCS).

[285]  Anant Agarwal,et al.  Scalar operand networks: on-chip interconnect for ILP in partitioned architectures , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[286]  José Duato.  A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks , 1995, IEEE Trans. Parallel Distributed Syst..

[287]  Rajeev Balasubramonian,et al.  Towards scalable, energy-efficient, bus-based on-chip networks , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[288]  Natalie D. Enright Jerger,et al.  Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs , 2014, IEEE Transactions on Computers.