A Management Strategy for the Reliability and Performance Improvement of MLC-Based Flash-Memory Storage Systems

Cost has been a major driving force in the development of the flash-memory technology. Because of this, serious challenges are now faced for future products on reliability and performance requirements. In this work, we propose a management strategy to resolve the reliability and performance problems of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of advanced multilevel cell flash-memory chips. The capability of the proposed approach is analyzed with reliability considerations and evaluated by experiments over realistic workloads with respect to the reliability and performance improvement.

[1]  Naehyuck Chang,et al.  Energy-aware memory allocation in heterogeneous non-volatile memory systems , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[2]  Sivan Toledo,et al.  Competitive Analysis of Flash-Memory Algorithms , 2006, ESA.

[3]  Tei-Wei Kuo,et al.  Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[4]  Naehyuck Chang,et al.  Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[5]  Michael Isard,et al.  A design for high-performance flash disks , 2007, OPSR.

[6]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[7]  Trevor N. Mudge,et al.  FlashCache: a NAND flash memory file cache for low power web servers , 2006, CASES '06.

[8]  Harold J. Larson.  Introduction to Probability , 1994 .

[9]  Yehua Du,et al.  Adaptive energy-aware design of a multi-bank flash-memory storage system , 2005, 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'05).

[10]  Tei-Wei Kuo,et al.  A NOR Emulation Strategy over NAND Flash Memory , 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

[11]  阿米尔·班.  Flash File System , 1994 .

[12]  Naehyuck Chang,et al.  Demand paging for OneNANDTM Flash eXecute-in-place , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[13]  Tei-Wei Kuo,et al.  An efficient management scheme for large-scale flash-memory storage systems , 2004, SAC '04.

[14]  Joonwon Lee,et al.  CFLRU: a replacement algorithm for flash memory , 2006, CASES '06.

[15]  Ronald L. Graham,et al.  Concrete mathematics - a foundation for computer science , 1991 .

[16]  Shin-Dug Kim,et al.  A new NAND-type flash memory package with smart buffer system for spatial and temporal localities , 2005, J. Syst. Archit..

[17]  Moon Jeung Joe,et al.  LGeDBMS: a small DBMS for embedded system with flash memory , 2006, VLDB.

[18]  Richard E. Parent,et al.  Computer animation - algorithms and techniques , 2012 .

[19]  Chanik Park,et al.  Energy-aware demand paging on NAND flash-based embedded storages , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[20]  Jin-Soo Kim,et al.  FAB: flash-aware buffer management policy for portable media players , 2006, IEEE Transactions on Consumer Electronics.

[21]  Tei-Wei Kuo,et al.  Energy-efficient and performance-enhanced disks using flash-memory cache , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[22]  Hiroshi Motoda,et al.  A Flash-Memory Based File System , 1995, USENIX.

[23]  Tei-Wei Kuo,et al.  Special Issues in Flash , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[24]  Tei-Wei Kuo,et al.  An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[25]  Tei-Wei Kuo,et al.  An adaptive striping architecture for flash memory storage systems of embedded systems , 2002, Proceedings. Eighth IEEE Real-Time and Embedded Technology and Applications Symposium.

[26]  David Woodhouse,et al.  JFFS : The Journalling Flash File System , 2001 .

[27]  Ronald L. Rivest,et al.  Introduction to Algorithms, Second Edition , 2001 .

[28]  Tei-Wei Kuo,et al.  A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[29]  Tei-Wei Kuo,et al.  An Efficient B-Tree Layer for Flash-Memory Storage Systems , 2003, RTCSA.

[30]  Li-Pin Chang,et al.  On efficient wear leveling for large-scale flash-memory storage systems , 2007, SAC '07.

[31]  Abraham Silberschatz,et al.  Operating System Concepts, Sixth Edition , 2002 .

[32]  Sivan Toledo,et al.  Storing a Persistent Transactional Object Heap on Flash Memory , 2006, IEEE International Conference on Software-Science, Technology & Engineering (SwSTE'07).

[33]  Carla Golla,et al.  Flash Memories , 1999 .

[34]  Hyojun Kim,et al.  BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage , 2008, FAST.