Fpga interconnect delay fault testing
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[1] Hideo Fujiwara,et al. A test methodology for interconnect structures of LUT-based FPGAs , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).
[2] Yervant Zorian,et al. Test of RAM-based FPGA: methodology and application to the interconnect , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[3] Jian Xu,et al. Design and implementation of a parity-based BIST scheme for FPGA global interconnects , 2001, Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555).
[4] Ping Chen,et al. Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) , 1996, Proceedings of 14th VLSI Test Symposium.
[5] Sying-Jyan Wang,et al. Testing and diagnosis of interconnect structures in FPGAs , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).
[6] Fabrizio Lombardi,et al. An approach for testing programmable/configurable field programmable gate arrays , 1996, Proceedings of 14th VLSI Test Symposium.
[7] Andrzej Krasniewski. Testing FPGA delay faults in the system environment is very different from "ordinary" delay fault testing , 2001, Proceedings Seventh International On-Line Testing Workshop.
[8] Yervant Zorian,et al. Different experiments in test generation for XILINX FPGAs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[9] Yervant Zorian,et al. Testing the Interconnect of RAM-Based FPGAs , 1998, IEEE Des. Test Comput..
[10] Hideo Ito,et al. Testing the logic cells and interconnect resources for FPGAs , 1999, Proceedings Eighth Asian Test Symposium (ATS'99).
[11] Charles E. Stroud,et al. BIST-Based Delay-Fault Testing in FPGAs , 2003, J. Electron. Test..
[12] Anurag Tiwari,et al. Hardware/software co-debugging for reconfigurable computing , 2000, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).
[13] Wayne M. Needham,et al. High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[14] Premachandran R. Menon,et al. BIST-based delay path testing in FPGA architectures , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).