Improved Decomposition of Signal Transition Graphs

Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. It has been suggested to decompose such a specification as a first step; this leads to a modular implementation, which can support circuit synthesis by possibly avoiding state explosion or allowing the use of library elements. In a previous paper, the originalmethod was extended and shown to bemuchmore generally applicable than known before. But further extensions are necessary, and some are presented in this paper. In particular, to avoid dynamic auto-conflicts, the previous paper insisted on avoiding structural autoconflicts, which is too restrictive; as a main contribution, we show how to work with the latter type of auto-conflicts. This extension makes it necessary to restructure presentation and correctness proof of the decomposition algorithm.

[1]  Roberto Segala.  Quiescence, Fairness, Testing, and the Notion of Implementation (Extended Abstract) , 1993, CONCUR.

[2]  Tam-Anh Chu.  On the models for designing VLSI asynchronous digital systems , 1986, Integr..

[3]  Chris J. Myers,et al.  Synthesis of speed independent circuits based on decomposition , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[4]  Charles André,et al.  Structural Transformations Giving B-Equivalent PT-Nets , 1982, European Workshop on Applications and Theory of Petri Nets.

[5]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[6]  Hugo De Man,et al.  A generalized signal transition graph model for specification of complex interfaces , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[7]  Alexandre Yakovlev,et al.  Signal Graphs: From Self-Timed to Timed Ones , 1985, PNPM.

[8]  S. Wenct.  Using Petri Nets in the Design Process for Interacting Asynchronous Sequential Circuits , 1977 .

[9]  Alex Kondratyev,et al.  Synthesis Method in Self-Timed Design Decompositional Approach , 1993 .

[10]  Walter Vogler,et al.  Component Refinement and CSC Solving for STG Decomposition , 2005, FoSSaCS.

[11]  Luciano Lavagno,et al.  On the models for asynchronous circuit behaviour with OR causality , 1996, Formal Methods Syst. Des..

[12]  Ralf Wollowski,et al.  CASCADE: A Tool Kernel Supporting a Comprehensive Design Method for Asynchronous Controllers , 2000, ICATPN.

[13]  Hartmut Ehrig,et al.  An Algebraic View on Petri Nets , 1997, Bull. EATCS.

[14]  Nancy A. Lynch,et al.  Distributed Algorithms , 1992, Lecture Notes in Computer Science.

[15]  Josep Carmona,et al.  ILP Models for the Synthesis of Asynchronous Control Circuits , 2003, ICCAD 2003.

[16]  Jo C. Ebergen,et al.  Arbiters: An Exercise in Specifying and Decomposing Asynchronously Communicating Components , 1992, Sci. Comput. Program..

[17]  Walter Vogler,et al.  Strategies for Optimised STG Decomposition , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).

[18]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .