An efficient statistical analysis methodology and its application to high-density DRAMs

In this work, a new approach for the statistical worst case of full-chip circuit performance and parametric yield prediction, using both the Modified-Principal Component Analysis (MPCA) and the Gradient Method (GM), is proposed and verified. This method enables designers not only to predict the standard deviations of circuit performances but also track the circuit performances associated with the process shift by measuring E-tests. This new method is validated experimentally during the development and production of high density DRAMs. Our contributions to statistical circuit design are as follows: 1) a method for directly generating a parametrized model associated with electrical test data 2) the first application to high density DRAMs using the true statistical method

[1]  M. Redford,et al.  Analysis of mixed-signal manufacturability with statistical TCAD , 1995, Proceedings of International Symposium on Semiconductor Manufacturing.

[2]  Soo-In Cho,et al.  A realistic methodology for the worst case analysis of VLSI circuit performances , 1996, 1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095).

[3]  S. M. Lewis,et al.  Orthogonal Fractional Factorial Designs , 1986 .

[4]  Sang-Hoon Lee,et al.  New model parameter extraction environment for the submicron circuit models , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[5]  G. Hachtel The simplicial approximation approach to design centering , 1977 .

[6]  Marc Rocchi,et al.  Realistic statistical worst-case simulations of VLSI circuits , 1991 .

[7]  Douglas C. Montgomery,et al.  Response Surface Methodology: Process and Product Optimization Using Designed Experiments , 1995 .

[8]  D. F. Morrison,et al.  Multivariate Statistical Methods , 1968 .

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  Computing parametric yield accurately and efficiently , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Ping Yang,et al.  Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits , 1985, IEEE Transactions on Electron Devices.

[11]  S.G. Duvall,et al.  A practical methodology for the statistical design of complex logic products for performance , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Mien Li,et al.  Computing parametric yield adaptively using local linear models , 1996, 33rd Design Automation Conference Proceedings, 1996.

[13]  Linda S. Milor,et al.  Computing parametric yield adaptively using local linear models , 1996, DAC '96.

[14]  D.L. Scharfetter,et al.  General optimization and extraction of IC device model parameters , 1983, IEEE Transactions on Electron Devices.

[15]  Costas J. Spanos,et al.  Parameter Extraction for Statistical IC Process Characterization , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Andrzej J. Strojwas,et al.  Statistical control of VLSI fabrication processes. II. A software system , 1988 .

[17]  Sung-Mo Kang,et al.  iEDISON: an interactive statistical design tool for MOS VLSI circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.