Multicast Parallel Pipeline Router Architecture for Network-on-Chip

This paper presents a flexible mesh router architecture using synchronous parallel pipeline worm-switching supporting unicast and multicast services. A very flexible mechanism to manage broadcast-flow to share the communication link in on-chip network is proposed. The proposed mechanism guarantees, that all flits in multicast packets can be accepted in their multiple destination nodes. Our network-on-chip (NoC) is implemented based on modular synthesizable VHDL objects. The architecture is flexible to design new NoC prototypes. Area overhead to update the NoC from unicast to multicast with the same routing algorithm is only about 15%.

[1]  Jens Sparsø,et al.  Implementation of guaranteed services in the MANGO clockless network-on-chip , 2006 .

[2]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[3]  Axel Jantsch,et al.  Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[5]  Luciano Lavagno,et al.  Asynchronous on-chip networks , 2005 .

[6]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[7]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[8]  Alain Greiner,et al.  A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[9]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[10]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[11]  Rudy Lauwereins,et al.  Topology adaptive network-on-chip design and implementation , 2005 .

[12]  Manfred Glesner,et al.  Deadlock-free routing and component placement for irregular mesh-based networks-on-chip , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[13]  Luca Benini,et al.  Network-on-chip architectures and design methods , 2005 .

[14]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[15]  Axel Jantsch,et al.  Connection-oriented multicasting in wormhole-switched networks on chip , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[16]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[17]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.