Modified Booth Multipliers With a Regular Partial Product Array
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Shiann-Rong Kuang | Jiun-Ping Wang | Cang-Yuan Guo | Shiann-Rong Kuang | Jiun-Ping Wang | Cang-Yuan Guo
[1] S. S. Choi,et al. Efficient design of modified Booth multipliers for predetermined coefficients , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[2] Vojin G. Oklobdzija,et al. General data-path organization of a MAC unit for VLSI implementation of DSP processors , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[3] Jalil Fadavi-Ardekani,et al. M*N Booth encoded multiplier generator using optimized Wallace trees , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[4] Chip-Hong Chang,et al. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] O. Hasan,et al. Automated formal synthesis of Wallace Tree multipliers , 2007, 2007 50th Midwest Symposium on Circuits and Systems.
[6] Chein-Wei Jen,et al. High-Speed Booth Encoded Parallel Multiplier Design , 2000, IEEE Trans. Computers.
[7] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[8] Milos D. Ercegovac,et al. High-performance low-power left-to-right array multiplier design , 2005, IEEE Transactions on Computers.
[9] Jean-Luc Gaudiot,et al. A Simple High-Speed Multiplier Design , 2006, IEEE Transactions on Computers.
[10] F. Elguibaly,et al. A fast parallel multiplier-accumulator using the modified Booth algorithm , 2000 .
[11] Minkyu Song,et al. Design of a high performance 32/spl times/32-bit multiplier with a novel sign select Booth encoder , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[12] Jalil Fadavi-Ardekani. M×N Booth encoded multiplier generator using optimized Wallace trees , 1993, IEEE Trans. Very Large Scale Integr. Syst..
[13] Shen-Fu Hsiao,et al. Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers , 1998 .
[14] E. Swartzlander,et al. Low power parallel multipliers , 1996, VLSI Signal Processing, IX.
[15] Heinrich Klar,et al. General algorithms for a simplified addition of 2's complement numbers , 1995, IEEE J. Solid State Circuits.