Architecture-level performance estimation for IP-based embedded systems

In this paper, we propose a architecture-level performance estimation method for IP-based embedded systems using system-level profiling. Our method enables the performance estimation by the following procedures: 1) System-level profiling. 2) Automatic construction of the execution dependency graph (EDG) from the profile information. 3) Estimation of the system performance based on the EDG analysis. Our method enables fast performance estimation because it can estimate the performance of various architectures from the same system-level profile information. Experimental results show that our estimation method is about 10,000 times faster than the architecture-level simulations.

[1]  M. Takahashi.  An efficient power and performance evaluation method with reconfigurable bus architecture Model , 2003 .

[2]  Daniel Gajski.  IP-based design methodology , 1999, DAC '99.

[3]  Ahmed Amine Jerraya,et al.  Automatic generation of fast timed simulation models for operating systems in SoC design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[4]  Edward A. Lee,et al.  Overview of the Ptolemy project , 2001 .

[5]  Tughrul Arslan,et al.  Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Luciano Lavagno,et al.  Concurrent execution semantics and sequential simulation algorithms for the Metropolis meta-model , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).