Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme

Spin-transfer torque magnetic random access memory (STT-MRAM) is an emerging nonvolatile memory technology and a potential candidate to replace CMOS-based on-chip memories. However, the bit-cell switching behavior is stochastic, which is further exacerbated due to the temperature and the process variation (PV) effects, leading to reliability failures. The conventional solution to mitigate such errors is to define the write margin based on the worst case conditions, however, this results in an excessive margin that prevents the usage of STT-MRAM in fast memories. This paper proposes to significantly reduce the write margin of STT-MRAM with no impact on the read latency, which is achieved by clustering the cache lines based on the manufactured STT-MRAM parameters and then exploiting the proposed opportunistic write approach (i.e., terminating the write process before all bit switchings are completed). This approach is supported by a novel Lazy error correcting code (Lazy-ECC), which is based on the fact that error detection is much faster than correction. Hence, the errors can be detected quickly and all erroneous data can be reverted before they arrive critical parts of the system (e.g., commit stage or memory ports). A nonuniform adaptive ECC approach to manage PV and temperature-dependent retention and read disturb failures at runtime has also been proposed. The proposed approach enables a reliable use of STT-MRAM technology for fast cache applications.