Gemini: An Optical Interconnection Network for Parallel Processing

The Gemini interconnect is a dual technology (optical and electrical) interconnection network designed for use in tightly-coupled multicomputer systems. It consists of a circuit-switched optical data path in parallel with a packet-switched electrical control/data path. The optical path is used for transmission of long data messages and the electrical path is used for switch control and transmission of short data messages. The paper describes the architecture of the interconnection network and related communications protocols. Fairness issues associated with network operation are addressed and a discrete-event simulation model of the entire system is described. Network performance characteristics derived from the simulation model are presented. The results show significant performance benefits when using virtual output queuing and quantify the tradeoffs between throughput and fairness in the system.

[1]  Jean C. Walrand,et al.  Achieving 100% throughput in an input-queued switch , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[2]  Abhay Parekh,et al.  A generalized processor sharing approach to flow control in integrated services networks-the multiple node case , 1993, IEEE INFOCOM '93 The Conference on Computer Communications, Proceedings.

[3]  Rami G. Melhem,et al.  A high speed scheduler/controller for unbuffered banyan networks , 2001, Comput. Commun..

[4]  Mark A. Franklin,et al.  The Gemini interconnect: Data path measurements and performance analysis , 1999, Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI).

[5]  Pedro López,et al.  A high performance router architecture for interconnection networks , 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.

[6]  Mark A. Franklin,et al.  Design of an optically-interconnected multiprocessor , 1998, Proceedings. Fifth International Conference on Massively Parallel Processing (Cat. No.98EX182).

[7]  Thomas E. Anderson,et al.  High-speed switch scheduling for local-area networks , 1993, TOCS.

[8]  QueueingJon,et al.  WF 2 Q : Worst-case Fair Weighted Fair , 1996 .

[9]  Lixia Zhang,et al.  VirtualClock: a new traffic control algorithm for packet-switched networks , 1991, TOCS.

[10]  Kenneth E. Batcher,et al.  The flip network in staran , 1976 .

[11]  C. Lund.  Optics inside future computers , 1997, Proceedings of the Fourth International Conference on Massively Parallel Processing Using Optical Interconnections.

[12]  Anthony S. Acampora,et al.  The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching , 1987, IEEE J. Sel. Areas Commun..

[13]  Rami G. Melhem,et al.  Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks , 1999, IEEE Trans. Computers.

[14]  George Varghese,et al.  Leap forward virtual clock: a new fair queuing scheme with guaranteed delays and throughput fairness , 1997, PODC '97.

[15]  Abhay Parekh,et al.  A generalized processor sharing approach to flow control in integrated services networks-the single node case , 1992, [Proceedings] IEEE INFOCOM '92: The Conference on Computer Communications.

[16]  George Varghese,et al.  Efficient fair queueing using deficit round robin , 1995, SIGCOMM '95.

[17]  Wilson C. Hsieh,et al.  Impulse: Memory system support for scientific applications , 1999, Sci. Program..

[18]  Scott Shenker,et al.  Analysis and simulation of a fair queueing algorithm , 1989, SIGCOMM '89.

[19]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[20]  Samuel P. Morgan,et al.  Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..

[21]  R. Srikant,et al.  Fair scheduling in wireless packet networks , 1997, SIGCOMM '97.

[22]  Nick McKeown,et al.  Scheduling algorithms for input-queued cell switches , 1996 .

[23]  David A. Patterson,et al.  Computer architecture (2nd ed.): a quantitative approach , 1996 .

[24]  Nick McKeown,et al.  On the speedup required for combined input- and output-queued switching , 1999, Autom..

[25]  Adam W. Bojanczyk,et al.  Design and Performance Evaluation of a Portable Parallel Library for Space-Time Adaptive Processing , 2000, IEEE Trans. Parallel Distributed Syst..

[26]  Hui Zhang,et al.  WF/sup 2/Q: worst-case fair weighted fair queueing , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[27]  Lixia Zhang.  VirtualClock: A New Traffic Control Algorithm for Packet-Switched Networks , 1991, ACM Trans. Comput. Syst..

[28]  Rami G. Melhem,et al.  Distributed, dynamic control of circuit-switched Banyan networks , 1998, Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing.

[29]  S. Jamaloddin Golestani,et al.  A self-clocked fair queueing scheme for broadband applications , 1994, Proceedings of INFOCOM '94 Conference on Computer Communications.

[30]  Mark A. Franklin,et al.  Fair scheduling in an optical interconnection network , 1999, MASCOTS '99. Proceedings of the Seventh International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.

[31]  Srinivasan Keshav,et al.  An Engineering Approach to Computer Networking: ATM Networks , 1996 .

[32]  Mark A. Franklin,et al.  Evaluating the performance of photonic interconnection networks , 2002, Proceedings 35th Annual Simulation Symposium. SS 2002.