论文信息 - 0.15 /spl mu/m CMOS process for high performance and high reliability

0.15 /spl mu/m CMOS process for high performance and high reliability

We have developed a novel 0.15 /spl mu/m CMOS process for high performance and high reliability, consisting of mixing the CoSi/sub 2/-Si interface using Si/sup +/ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using these processes, the propagation delay time of 21 psec/stage was obtained for a 0.15 /spl mu/m CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.<<ETX>>

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