Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between pand n-functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including NAND/NOR, AND/OR, and XOR/XNOR, and compared them with classical implementations. Two 1-bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.

[1]  S.C. Rustagi,et al.  High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices , 2006, IEEE Electron Device Letters.

[2]  D. Klaassen,et al.  A new recombination model for device simulation including tunneling , 1992 .

[3]  Wei Tang,et al.  Ultrashort channel silicon nanowire transistors with nickel silicide source/drain contacts. , 2012, Nano letters.

[4]  J. Knoch,et al.  High-performance carbon nanotube field-effect transistor with tunable polarities , 2005, IEEE Transactions on Nanotechnology.

[5]  G. De Micheli,et al.  Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.

[6]  Thomas Mikolajick,et al.  Direct probing of Schottky barriers in Si nanowire Schottky barrier field effect transistors. , 2011, Physical review letters.

[7]  Mike Golio,et al.  Fifty Years of Moore's Law , 2015, Proc. IEEE.

[8]  Rui Zhang,et al.  Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[9]  Thomas Mikolajick,et al.  Dually active silicon nanowire transistors and circuits with equal electron and hole transport. , 2013, Nano letters.

[10]  Giovanni De Micheli,et al.  Efficient arithmetic logic gates using double-gate silicon nanowire FETs , 2013, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS).

[11]  Stefan Slesazeck,et al.  Reconfigurable silicon nanowire transistors. , 2012, Nano letters.

[12]  Thomas Mikolajick,et al.  Reconfigurable Nanowire Electronics-Enabling a Single CMOS Circuit Technology , 2014, IEEE Transactions on Nanotechnology.

[13]  Luca Gaetano Amarù,et al.  Nanowire systems: technology and design , 2014, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences.

[14]  Giovanni De Micheli,et al.  Advanced system on a chip design based on controllable-polarity FETs , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[15]  Stefan Slesazeck,et al.  Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors , 2014, IEEE Electron Device Letters.

[16]  Pascal Gentile,et al.  Multifunctional devices and logic gates with undoped silicon nanowires. , 2012, Nano letters.

[17]  Frédéric Gaffiot,et al.  Design of a Novel CNTFET-based Reconfigurable Logic Gate , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[18]  Frédéric Gaffiot,et al.  CNTFET Modeling and Reconfigurable Logic-Circuit Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  I. Hassoune,et al.  Double-gate MOSFET based reconfigurable cells , 2007 .

[20]  Moshe Y. Vardi.  Moore's law and the sand-heap paradox , 2014, CACM.

[21]  Dieter Fuhrmann,et al.  Logical Effort Designing Fast Cmos Circuits , 2016 .

[22]  Udo Schwalke,et al.  Reconfigurable CMOS with undoped silicon nanowire midgap Schottky-barrier FETs , 2013, Microelectron. J..

[23]  T. Ghani,et al.  Proposal of a Spin Torque Majority Gate Logic , 2010, IEEE Electron Device Letters.

[24]  Giovanni De Micheli,et al.  Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Stefan Slesazeck,et al.  Material Prospects of Reconfigurable Transistor (RFETs) – From Silicon to Germanium Nanowires , 2014 .