Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

The electrical characteristics (C-V and I-V) of n+ - and p+ -polysilicon-gated ultrathinoxide capacitors and FETs were studied extensively to determine oxide thickness and to evaluate tunneling current. A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects. It allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves. With a chip standby power of ≤0.1 W per chip, direct tunneling current can be tolerated down to an oxide thickness of 15-20 A. However, transconductance reduction due to polysilicon depletion and finite inversion layer width effects becomes more severe for thinner oxides. The quantum-mechanical model predicts higher threshold voltage than the classical model, and the difference increases with the electric field strength at the silicon/oxide interface.

[1]  Y. Taur,et al.  Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's , 1997, IEEE Electron Device Letters.

[2]  H. Wong,et al.  CMOS scaling into the nanometer regime , 1997, Proc. IEEE.

[3]  J.D. Bude,et al.  Gate capacitance attenuation in MOS devices with thin gate dielectrics , 1996, IEEE Electron Device Letters.

[4]  S. Tiwari,et al.  Self‐consistent modeling of accumulation layers and tunneling currents through very thin oxides , 1996 .

[5]  Hiroshi Iwai,et al.  Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[6]  R. Rios,et al.  Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[7]  B. Riccò,et al.  Quantum-mechanical modeling of accumulation layers in MOS structure , 1992 .

[8]  H. Lifka,et al.  Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs , 1992 .

[9]  Yasuyuki Ohkura,et al.  Quantum effects in Si n-MOS inversion layer at high substrate concentration , 1990 .

[10]  Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process , 1988, Technical Digest., International Electron Devices Meeting.

[11]  B. Riccò,et al.  Oxide-thickness determination in thin-insulator MOS structures , 1988 .

[12]  C. Moglestue,et al.  Self‐consistent calculation of electron and hole inversion charges at silicon–silicon dioxide interfaces , 1986 .

[13]  S. Ghandhi,et al.  The theory and practice of microelectronics , 1984 .

[14]  G. Baccarani,et al.  Transconductance degradation in thin-Oxide MOSFET's , 1983, IEEE Transactions on Electron Devices.

[15]  Z. Weinberg,et al.  On tunneling in metal‐oxide‐silicon structures , 1982 .

[16]  K. Lehovec,et al.  Analysis of C-V data in the accumulation regime of MIS structures , 1976 .

[17]  C. Sah,et al.  Determination of the MOS oxide capacitance , 1975 .

[18]  J. Maserjian,et al.  Tunneling in thin MOS structures , 1974 .

[19]  F. Stern.  Self-Consistent Results for n -Type Si Inversion Layers , 1972 .

[20]  J. Simmons.  Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film , 1963 .