A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.

[1]  C.-K.K. Yang,et al.  Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops , 2002, IEEE J. Solid State Circuits.

[2]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[3]  Chih-Kong Ken Yang,et al.  A Cmos 500 Mbps/pin Synchronous Point to Point Link Interface , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[4]  J. Sonntag,et al.  A monolithic CMOS 10 MHz DPLL for burst-mode data retiming , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[5]  Jieh-Tsorng Wu,et al.  A 125MHz 8b digital-to-phase converter , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[6]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[7]  Thomas H. Lee,et al.  A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM , 1994, IEEE J. Solid State Circuits.

[8]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[9]  P. Raha.  A 0.6-4.2V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nm CMOS process , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[10]  Pavan Kumar Hanumolu,et al.  Analysis of charge-pump phase-locked loops , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Un-Ku Moon,et al.  A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[12]  Behzad Razavi,et al.  Design techniques for low-voltage high-speed digital bipolar circuits , 1994 .

[13]  Ashoke Ravi,et al.  8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3/sup rd/ order, 3/5-bit IIR and 3/sup rd/ order 3-bit-FIR noise shapers in 90nm CMOS , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[14]  John A. McNeill.  Jitter in ring oscillators , 1997 .

[15]  M. Horowitz,et al.  Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[16]  B. Miller,et al.  A multiple modulator fractional divider , 1990, 44th Annual Symposium on Frequency Control.

[17]  Beomsup Kim,et al.  A low-noise fast-lock phase-locked loop with adaptive bandwidth control , 2000, IEEE Journal of Solid-State Circuits.

[18]  Stefanos Sidiropoulos,et al.  A semidigital dual delay-locked loop , 1997, IEEE J. Solid State Circuits.