K-밴드 CMOS 저잡음 증폭기의 최적 설계

In this paper, we present a design optimization technique of CMOS low noise amplifier (LNA) above 20 ㎓. The optimum gate width is derived for shunt input matching topology. Additionally the layout optimization is performed using multiple common-source FETs. Based on the proposed technique, the CMOS LNA operating at 24 ㎓ is designed using 0.18-㎛ CMOS technology. Simulation results show a noise figure of 2.4 ㏈ with a power gain of 16.6 ㏈ for l1.1㎽ power consumption.