Valid clocking in wavepipelined circuits

In this paper, we consider theproblemof clocking wavepipelined circuits. Wavepipelined circuits can operate at a much higher clock rate than conventionalpipelined circuits, because its maximum rate is limited only by the path delay difference instead of the maximum path delay, [Cot69]. Current research in this area has focused on minimizing the path delay difference, hence maximizing the achievable clock frequency. In this paper, we present an analysis of valid clock rates in wavepipelined circuits using a technique called Timed Boolean Functions. We show that the valid intervals for the clock period can be disconnected. Thus, it is insuf$cient to only know the minimum valid clock period in guaranteeing proper operation of pipelined circuits. We provide analytic expressionsfor the valid clock intervals in terms of both topological delay as well as Z-vector longest and shortest delays. Also uncertainties arising from manufacturing are taken into account. We also illustrate some potential difhculties in computing the exact valid clock intervals by demonstrating discontinuity and non-monotonicity of the harmonic number H(r) (the number of valid simultaneous data waves allowed) as a function of the clock period r. that, even in the presence of uncertainties of the physical world, analysis of wave pipelines can be done with relatively little effort and without timing diagrams. Further, we address some fundamental issues. First, since previous research focuses only on the maximum clock frequencies, we investigate whether the pipelined circuit will operate at any clock frequency less than the maximum clock frequency? If not, how can the valid clocking intervals be found? Second, given a clock frequency, how do we know whether it is valid and what function is the circuit computing at this frequency? 2 Wavepipelining in Pipeline Circuit Figure 1 shows a block diagram of a pipelined circuit.