Reconfigurable DeltaSigma modulator topology design through hierarchical mapping and constraint extraction

This paper presents a novel methodology for designing reconfigurable continuous-time @D@S modulator topologies while considering circuit-level implementation constraints. Topologies are optimized for minimizing their structural complexity, maximizing their robustness with respect to circuit nonidealities, and maximizing the feasibility of their circuit-level implementation. A case study for a three mode reconfigurable @D@S modulator shows that the produced topologies avoid circuit-level implementation difficulties existing in other approaches.

[1]  E. Sanchez-Sinencio,et al.  A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[2]  Piet Wambacq,et al.  Distortion analysis of analog integrated circuits , 1998 .

[3]  Ranga Vemuri,et al.  Component characterization and constraint transformation based on directed intervals for analog synthesis , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[4]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .

[5]  Ko-chi Kuo,et al.  A linear MOS transconductor using source degeneration and adaptive biasing , 2001 .

[6]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[7]  Bernhard E. Boser,et al.  The design of sigma-delta modulation analog-to-digital converters , 1988 .

[8]  H. Alan Mantooth,et al.  Modeling nonlinear dynamics in analog circuits via root localization , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[10]  Alex Doboli,et al.  Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[11]  Maria del Mar Hershenson,et al.  Automated optimal design of switched-capacitor filters , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[12]  Alex Doboli,et al.  MINLP based topology synthesis for delta sigma modulators optimized for signal path complexity, sensitivity and power consumption , 2005, Design, Automation and Test in Europe.

[13]  Edoardo Charbon,et al.  A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits , 1993 .

[14]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[15]  Lucien Breems,et al.  Continuous-Time Sigma-Delta Modulation for IF A/D Conversion in Radio Receivers , 2001 .

[16]  Tai-Haur Kuo,et al.  Automatic coefficients design for high-order sigma-delta modulators , 1999 .

[17]  Kush Gulati,et al.  A low-power reconfigurable analog-to-digital converter , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[18]  Alex Doboli,et al.  Systematic development of analog circuit structural macromodels through behavioral model decoupling , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[19]  R. V. Veldhoven A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[20]  C. S. Petrie,et al.  A multibit sigma-delta ADC for multimode receivers , 2003, IEEE J. Solid State Circuits.

[21]  Ángel Rodríguez-Vázquez,et al.  Top-Down Design of High-Performance Sigma-Delta Modulators , 1998 .

[22]  Rob A. Rutenbar,et al.  A mixed-integer nonlinear programming approach to analog circuit synthesis , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[23]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[24]  Maurits Ortmanns,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 80 dB dynamic range , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[25]  Georges G. E. Gielen,et al.  A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Rob A. Rutenbar,et al.  Computer-aided design of analog and mixed-signal integrated circuits , 2000, Proceedings of the IEEE.

[27]  Georges G. E. Gielen,et al.  An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  Stephen P. Boyd,et al.  Optimal design of a CMOS op-amp via geometric programming , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Alex Doboli,et al.  Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  William M. Skones,et al.  A continuous time delta sigma modulator , 2001 .

[31]  R.H.M. van Veldhoven A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003 .

[32]  Michel Steyaert,et al.  Optimal parameters for /spl Delta//spl Sigma/ modulator topologies , 1998 .

[33]  K. Philips,et al.  A 3.3 mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18 /spl mu/m CMOS with 70 dB dynamic range in 2 MHz bandwidth , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).