P-Channel MOSFETs on 4H-SiC {0001} and Nonbasal Faces Fabricated by Oxide Deposition and $\hbox{N}_{2}\hbox{O}$ Annealing

In this paper, we have investigated 4H-SiC p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with deposited SiO2 followed by N2O annealing. In addition to deposited oxides, dry-O2-grown oxides and N2O-grown oxides were also adopted as the gate oxides of SiC p-channel MOSFETs. The MOSFETs have been fabricated on the 4H-SiC (0001), (0001macr), (033macr8), and (112macr0) faces. The (0001) MOSFETs with deposited oxides exhibited a relatively high channel mobility of 10 cm2/V ldr s, although a mobility of 7 cm2/V ldr s was obtained in the (0001) MOSFETs with N2O-grown oxides. The channel mobility was also increased by utilizing the deposited SiO2 in the MOSFETs fabricated on nonbasal faces, although the MOSFETs on (0001macr) were not operational. Compared with the thermally grown oxides, the deposited oxides annealed in N2O are effective in improving the performance of 4H-SiC p-channel MOSFETs.

[1]  T. Kimoto,et al.  N2O-grown oxides/4H-SiC (0001), (0338), and (1120) interface properties characterized by using p-type gate-controlled diodes , 2008 .

[2]  T. Kimoto,et al.  Improved Performance of 4H-SiC Double Reduced Surface Field Metal–Oxide–Semiconductor Field-Effect Transistors by Increasing RESURF Doses , 2008 .

[3]  Y. Nakao,et al.  TDDB Measurement of Gate SiO2 on 4H-SiC Formed by Chemical Vapor Deposition , 2008 .

[4]  T. Kimoto,et al.  4H-SiC MIS Capacitors and MISFETs With Deposited $\hbox{SiN}_{x}/ \hbox{SiO}_{2}$ Stack-Gate Structures , 2008, IEEE Transactions on Electron Devices.

[5]  A. Agarwal,et al.  9 kV 4H-SiC IGBTs with 88 mΩ·cm2 of R diff, on , 2007 .

[6]  S. Hino,et al.  Fabrication and Characterization of 4H-SiC MOSFET with MOCVD-Grown Al2O3 Gate Insulator , 2007 .

[7]  S. Ryu,et al.  Optimizing the Thermally Oxidized 4H-SiC MOS Interface for P-Channel Devices , 2007 .

[8]  J. Cooper,et al.  High-Voltage Self-Aligned p-Channel DMOS-IGBTs in 4H-SiC , 2007, IEEE Electron Device Letters.

[9]  T. Kimoto,et al.  4H–SiC Lateral Double RESURF MOSFETs With Low on Resistance , 2007, IEEE Transactions on Electron Devices.

[10]  K. Suzuki,et al.  1.8 mΩcm2, 10 A Power MOSFET in 4H-SiC , 2006, 2006 International Electron Devices Meeting.

[11]  H. Matsunami,et al.  Improved Dielectric and Interface Properties of 4H-SiC MOS Structures Processed by Oxide Deposition and N2O Annealing , 2006 .

[12]  S. Tanimoto Impact of Dislocations on Gate Oxide in SiC MOS Devices and High Reliability ONO Dielectrics , 2006 .

[13]  T. Fuyuki,et al.  Characterization of 4H-SiC MOSFETs with NO-Annealed CVD Oxide , 2006 .

[14]  K. Fukuda,et al.  Effect of the oxidation process on the electrical characteristics of 4H–SiC p-channel metal-oxide-semiconductor field-effect transistors , 2006 .

[15]  T. Oomori,et al.  Successful Development of 1.2 kV 4H-SiC MOSFETs with the Very Low On-Resistance of 5 mΩcm2 , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[16]  T. Kimoto,et al.  Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs , 2005, IEEE Transactions on Electron Devices.

[17]  J. Cooper,et al.  A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC , 2004, IEEE Transactions on Electron Devices.

[18]  A. Agarwal,et al.  10-kV, 123-mOcm2 4H-SiC power DMOSFETs , 2004 .

[19]  A. Agarwal,et al.  10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC power DMOSFETs , 2004, IEEE Electron Device Letters.

[20]  A. Agarwal,et al.  10 kV, 123 m/spl Omega/-cm/sup 2/ 4H-SiC power DMOSFETs , 2004, Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC..

[21]  H. Matsunami,et al.  Electronic behaviors of high-dose phosphorus-ion implanted 4H-SiC(0001) , 2004 .

[22]  S. Dimitrijev,et al.  A P-Channel MOSFET on 4H-SiC , 2004 .

[23]  Kenji Fukuda,et al.  Effect of gate oxidation method on electrical properties of metal-oxide-semiconductor field-effect transistors fabricated on 4H-SiC C(0001) face , 2004 .

[24]  P. Friedrichs,et al.  4H-SiC Power MOSFET Blocking 1200V with a Gate Technology Compatible with Industrial Applications , 2003 .

[25]  Sei-Hyung Ryu,et al.  High temperature SiC trench gate p-IGBTs , 2003 .

[26]  S. Banerjee,et al.  1300-V 6H-SiC lateral MOSFETs with two RESURF zones , 2002, IEEE Electron Device Letters.

[27]  M. Melloch,et al.  Status and prospects for SiC power MOSFETs , 2002 .

[28]  Tsunenobu Kimoto,et al.  4H-SiC MOSFETs on (03-38) Face , 2002 .

[29]  John W. Palmour,et al.  N2O Processing Improves the 4H-SiC:SiO2 Interface , 2002 .

[30]  S. Dimitrijev,et al.  Effects of nitridation in gate oxides grown on 4H-SiC , 2001 .

[31]  O. W. Holland,et al.  Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide , 2001, IEEE Electron Device Letters.

[32]  Y. Sugawara,et al.  High channel mobility in inversion layers of 4H-SiC MOSFETs by utilizing (112~0) face , 1999, IEEE Electron Device Letters.

[33]  Kevin T. Kornegay,et al.  Recent progress of submicron CMOS using 6H-SiC for smart power applications , 1999 .

[34]  H. Matsunami,et al.  Effects of wet oxidation/anneal on interface properties of thermally oxidized SiO/sub 2//SiC MOS system and MOSFET's , 1999 .

[35]  Tsunenobu Kimoto,et al.  Step-controlled epitaxial growth of SiC: High quality homoepitaxy , 1997 .

[36]  A. S. Grove,et al.  Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditions , 1966 .

[37]  Sei-Hyung Ryu,et al.  Development of A 4H-SiC CMOS Inverter , 2006 .