PCS layout inductance modeling based on a time domain measurement approach

This paper presents a time domain measurement method to estimate the parasitic inductance of a Printed Circuit Board (PCB) layout. It is based on a lumped element model. The proposed measurement technique is also used for measuring the Equivalent Series Inductance (ESL) of devices such as low ohmic MOSFETs and high current shunt resistors. The PCB layout of a half bridge circuit is characterised as an application example.

[1]  Xuejun Fan,et al.  Emerging MOSFET packaging technologies and their thermal evaluation , 2002, ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258).

[2]  A. Sawle,et al.  Novel power MOSFET packaging technology doubles power density in synchronous buck converters for next generation microprocessors , 2002, APEC. Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.02CH37335).

[3]  F.B.J. Leferink,et al.  Inductance of printed circuit board ground planes , 1993, 1993 International Symposium on Electromagnetic Compatibility.

[4]  Heyno Garbe,et al.  Reduction of MoM matrix dimension by transmission line and circuit theory , 2001, 2001 IEEE EMC International Symposium. Symposium Record. International Symposium on Electromagnetic Compatibility (Cat. No.01CH37161).

[5]  T. Duerbaum,et al.  De-embedding of reverse recovery losses in fast switching VRM applications , 2003, Eighteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2003. APEC '03..

[6]  G. Verneau,et al.  Power MOSFET switching waveforms: an empirical model based on a physical analysis of charge locations , 2002, 2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference. Proceedings (Cat. No.02CH37289).