HiLeS2: model driven embedded system virtual prototype generation

Embedded system virtual prototyping allows exploration of solutions in system architecture and hardware specification, prior to real prototype construction, resulting in higher quality products, shorter time to market and cost reduction. Virtual prototypes allow simulation of the system so designers can analyze and evaluate their design decisions against system response. However, benefits in costs, shorter developing times and simulation capabilities can be affected by Virtual Prototype (VP) construction and modification, especially if done directly in Hardware Description Languages (HDL). The reasons are associated with being a manual error prone activity, the difficulty on keeping the VP in conformance to design requirements and the risk of simulations being hard to analyze. We propose a Model-Driven approach to generate automatically from a SysML high-level specification, structure and behavior, a VP in a HDL. Our proposal aims at providing a design methodology, significantly reducing the amount of manual code to diminish errors and increase simulation to design traceability. In our approach, we use a pivot language called HiLeS which is based on a Petri Net formalism facilitating the transformation into the HDL and allowing behavior verification. The paper presents the methodology and the model transformations done, specifically, to obtain from SysML sequence diagrams Petri Net models.