Technology Mapping for Low Power

The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.

[1]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[2]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[3]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[4]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .

[5]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[6]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[7]  Robert K. Brayton,et al.  Performance-oriented technology mapping , 1990 .

[8]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD 1992.

[9]  Farid N. Najm,et al.  Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[10]  Ibrahim N. Hajj,et al.  Maximum current estimation in CMOS circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.