High performance multi-transform coding hardware architecture design for H.264/AVC

In hardware architecture design,in order to increase the hardware utilization and minimize the hardware cost,and maintain the real-time coding at the same time,a multiple transform coding architecture which could process all the transforms in H.264/AVC was proposed.By simplifying these transforms and exploring their similarities,the proposed design merges the architectures processing individual transforms into a multi-transform coding architecture.Simulation and synthesis show that compared with other designs,this design has lower hardware cost,and can meet the requirement of real-time coding/decoding HD 1080i(1 920×1 088@60 fps) video at 50 MHz,which helps to reduce the power consumption.This architecture can be easily adjusted to achieve different data processing rates,so that it can be embedded into H.264/AVC coding systems of various data processing rates.