A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

In this brief, a self-aligned electrically separable double-gate (SA ESDG) MOS transistor technology is proposed and demonstrated. The SA ESDG structure is implemented by defining a dummy top gate that is self-aligned to the bottom gate and then later replacing the dummy using a real top gate. The proposed process is applied to the single-grain Si film formed by recrystallizing a low-pressure chemical vapor deposition a-Si with a metal induced unilateral crystallization technique and enhancing the grain sizes in a subsequent high temperature annealing step. The ideal device structure resulting from the process is verified by scanning electron microscope imaging. The good current-voltage characteristics and the noticeable dynamic threshold voltage effects are also observed in the implemented SA ESDG device.

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