Reconfigurable processor architectures: Varieties and representations

Reconfigurable processors combine the speed of application specific integrated circuits (ASIC) and the universality of classical digital processors by means of adaptability to the currently executed code. There is a great number of varieties in today's reconfigurable processor architectures. Processor architectures can be specified in many ways. Architecture specifications are usually used during the architecture design phase and in software tools such as compilers and simulators. The aim of this paper is to propose various comparison criteria for reconfigurable processor architectures and to give an overview of the specification methods for them. The main contribution of this paper is a proposal of the new ontology-based representation of reconfigurable processor architectures.

[1]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[2]  Bjorn De Sutter,et al.  Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array , 2008, HiPEAC.

[3]  B. V. Essen,et al.  Designing a Coarse-grained Reconfigurable Architecture for Power Efficiency ∗ , 2007 .

[4]  Gerald Estrin,et al.  Reconfigurable Computer Origins: The UCLA Fixed-Plus-Variable (F+V) Structure Computer , 2002, IEEE Ann. Hist. Comput..

[5]  Yarden Katz,et al.  Pellet: A practical OWL-DL reasoner , 2007, J. Web Semant..

[6]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[7]  Seth Copen Goldstein,et al.  Tartan: evaluating spatial computation for whole program execution , 2006, ASPLOS XII.

[8]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  Rainer Leupers,et al.  High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures , 2008, 2008 Design, Automation and Test in Europe.

[10]  Holger Knublauch,et al.  The Protégé OWL Plugin: An Open Development Environment for Semantic Web Applications , 2004, SEMWEB.

[11]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[12]  Mahmood Ahmadi,et al.  Reconfigurable computing architecture survey and introduction , 2009, 2009 2nd IEEE International Conference on Computer Science and Information Technology.

[13]  Georgi Gaydadjiev,et al.  Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array , 2007, ARC.

[14]  Carl Ebeling,et al.  A Type Architecture for Hybrid Micro-Parallel Computers , 2006, FCCM.

[15]  Rudy Lauwereins,et al.  DRESC: a retargetable compiler for coarse-grained reconfigurable architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[16]  Nachiket Kapre,et al.  Packet Switched vs. Time Multiplexed FPGA Overlay Networks , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[17]  Wendy Hall,et al.  The Semantic Web Revisited , 2006, IEEE Intelligent Systems.

[18]  Pedro C. Diniz,et al.  Compilation Techniques for Reconfigurable Architectures , 2008 .

[19]  Raphael Volz,et al.  Cooking the Semantic Web with the OWL API , 2003, SEMWEB.

[20]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[21]  Carl Ebeling,et al.  SPR: an architecture-adaptive CGRA mapping tool , 2009, FPGA '09.

[22]  Ian Horrocks,et al.  FaCT++ Description Logic Reasoner: System Description , 2006, IJCAR.

[23]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[24]  Peter F. Patel-Schneider,et al.  OWL 2 Web Ontology Language Primer (Second Edition) , 2012 .

[25]  Ming Cong,et al.  Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology , 2009, 2009 International Joint Conference on Computational Sciences and Optimization.

[26]  Maya Gokhale,et al.  Trident: From High-Level Language to Hardware Circuitry , 2007, Computer.

[27]  Wayne Luk,et al.  Reconfigurable computing: architectures and design methods , 2005 .

[28]  Russell Tessier,et al.  c ○ 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Reconfigurable Computing for Digital Signal Processing: A Survey ∗ , 1999 .