VLSI implementation of a feature mapping neural network
暂无分享,去创建一个
Modification of Kohonen's self-organizing feature map algorithm and its dedicated parallel hardware implementation are the focus of this paper. This work is motivated by the need to implement a 5/spl times/5 neural network using digital standard cells and high level VLSI system design tools. The neural net considered is a two layered, feed forward architecture that learns relationships among unknown input data patterns. The prototype system consists of 25 processing units (neurons). Each processing unit operates at 10 MHz. Communication among processing units is accomplished using a broadcast bus. Performance of the system is estimated to be 110,000 iterations per second.<<ETX>>
[1] Douglas S. Reeves,et al. The TInMANN VLSI chip , 1992, IEEE Trans. Neural Networks.
[2] Jorma Laaksonen,et al. Variants of self-organizing maps , 1990, International 1989 Joint Conference on Neural Networks.
[3] T. Yamada,et al. A self-learning neural network chip with 125 neurons and 10 K self-organization synapses , 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.