Physical Design of Printed Circuit Boards: Group Technology Approach

In this chapter, the applicability of Group Technology models and clustering techniques of the industrial engineering and operation research community to the partitioning problem of electronic circuits is examined. The problem is shown to be NP-complete, hence intractable within most modern computing environments. Characteristics of the solution are outlined and a grouping heuristic algorithm is discussed. We derive lower bounds on the objective function for any set of constraints on pairs of gates that must be in the same chip. The lower bounds and the grouping heuristic procedure are used to develop a branch and bound algorithm. Finally, computational results are given for four test problems.

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