Influence of lot arrival distribution on production dispatching rule scheduling and cost in the final test process of LSI manufacturing system

Seven production dispatching rules in the real final test process of one-chip microcomputers are evaluated through an event-driven simulation analysis with regard to the total number of processed lots, the number of tardy lots, the average turnaround time (TAT) and the cost per chip. Several lot arrival distributions during one month are assumed to simulate the fact that the arrival lots tend to increase toward the end of the month but drop near the beginning of the next month. Simulated results for six months show that the rule which considers the time required for jig exchange, the time required for temperature change, the lot waiting time in queue and also the remaining processing time of the machine in use is superior to others. The rule processes about 99% of the planned number of lots and the ratio of tardy lots to processed lots is less than 1%, even when the deviation of lot arrival distribution with respect to the uniform distribution changes from 0% to 50%. The average test TAT and the test cost per chip are about 5% and 70% with respect to those for the well-known first-in first-out (FIFO) rule.