An NMOS voltage reference

An NMOS temperature-stable voltage reference, affording - in breadboard results - a temperature drift of less than 6 PPM/°C, will be described. Calculations show that less than 2 PPM/°C can be achieved with proper choice of device geometries.

[1]  G. Taylor,et al.  Modeling of an ion-implanted silicon-gate depletion-mode IGFET , 1975, IEEE Transactions on Electron Devices.

[2]  P.P. Wang,et al.  Double boron implant short-channel MOSFET , 1977, IEEE Transactions on Electron Devices.