A new fault-tolerant and congestion-aware adaptive routing algorithm for regular Networks-on-Chip

In this paper, we propose a new fault-tolerant and congestion-aware adaptive routing algorithm for Networks-on-Chip (NoCs). The proposed algorithm is based on the ball-and-string model and employs a distributed approach based on partitioning of the regular NoC architecture into regions controlled by local monitoring units. Each local monitoring unit runs a shortest path computation procedure to identify the best routing path so that highly congested routers and faulty links are avoided while latency is improved. To dynamically react to continuously changing traffic conditions, the shortest path computation procedure is invoked periodically. Because this procedure is based on the ball-and-string model, the hardware overhead and computational times are minimal. Experimental results based on an actual Verilog implementation demonstrate that the proposed adaptive routing algorithm improves significantly the network throughput compared to traditional XY routing and DyXY adaptive algorithms.

[1]  David Blaauw,et al.  Vicis: A reliable network for unreliable silicon , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[2]  Yutaka Arakawa,et al.  New Parallel Shortest Path Searching Algorithm based on Dynamically Reconfigurable Processor DAPDNA-2 , 2007, 2007 IEEE International Conference on Communications.

[3]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[4]  Ming Li,et al.  DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[5]  Radu Marculescu.  Networks-on-chip: the quest for on-chip fault-tolerant communication , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[6]  Ning Wu,et al.  A network monitor based dynamic routing scheme for Network on Chip , 2009, 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia).

[7]  Kai-Yeung Siu,et al.  New dynamic SPT algorithm based on a ball-and-string model , 1999, IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320).

[8]  Erik B. van der Tol,et al.  Mapping of MPEG-4 decoding on a flexible architecture platform , 2001, IS&T/SPIE Electronic Imaging.

[9]  Yingtao Jiang,et al.  Fault-tolerant routing schemes in RDT(2,2,1)//spl alpha/-based interconnection network for networks-on-chip design , 2005, 8th International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'05).

[10]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[11]  Luca Benini,et al.  A method to remove deadlocks in Networks-on-Chips with Wormhole flow control , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[12]  David Blaauw,et al.  A highly resilient routing algorithm for fault-tolerant NoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[13]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[14]  Vittorio Zaccaria,et al.  Yield enhancement by robust application-specific mapping on network-on-chips , 2009, 2009 2nd International Workshop on Network on Chip Architectures.

[15]  Jorg Henkel,et al.  Run-time adaptive on-chip communication scheme , 2007, ICCAD 2007.

[16]  Fernando Gehm Moraes,et al.  A path-load based adaptive routing algorithm for networks-on-chip , 2009, SBCCI.

[17]  Hideharu Amano,et al.  A Lightweight Fault-Tolerant Mechanism for Network-on-Chip , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[18]  Lei Gao,et al.  An accurate and efficient performance analysis approach based on queuing model for network on chip , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[19]  Wayne Luk,et al.  A DP-network for optimal dynamic routing in network-on-chip , 2009, CODES+ISSS '09.

[20]  Tuo Shi,et al.  An O(L) Parallel Shortest Path Algorithm , 2009, CDES.

[21]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[22]  Axel Jantsch,et al.  A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip , 2010, NoCArc '10.

[23]  Vincenzo Catania,et al.  Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip , 2008, IEEE Transactions on Computers.