RDE-based transistor-level gate simulation for statistical static timing analysis
暂无分享,去创建一个
Qin Tang | Amir Zjajo | Michel Berkelaar | N. P. van der Meijs | A. Zjajo | Qin Tang | Michel Berkelaar | Nick van der Meijs
[1] A.B. Kahng,et al. Statistical Gate Level Simulation via Voltage Controlled Current Source Models , 2006, 2006 IEEE International Behavioral Modeling and Simulation Workshop.
[2] Murat R. Becer,et al. Transistor level gate modeling for accurate and fast timing, noise, and power analysis , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[3] Shahin Nazarian,et al. Statistical logic cell delay analysis using a current-based model , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[4] Peng Li,et al. A waveform independent gate model for accurate timing analysis , 2005, 2005 International Conference on Computer Design.
[5] Yehea I. Ismail,et al. Weibull-based analytical waveform model , 2003, IEEE Trans. on CAD of Integrated Circuits and Systems.
[6] Sung-Mo Kang,et al. Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics , 1994, ICCAD.
[7] Ishiuchi,et al. Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .
[8] Min Chen,et al. Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[9] Sarma B. K. Vrudhula,et al. Current source based standard cell model for accurate signal integrity and timing analysis , 2008, 2008 Design, Automation and Test in Europe.
[10] N. Bershad,et al. Random differential equations in science and engineering , 1975, Proceedings of the IEEE.
[11] Angelo Brambilla,et al. Recasting modified nodal analysis to improve reliability in numerical circuit Simulation , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.
[12] Noel Menezes,et al. A multi-port current source model for multiple-input switching effects in CMOS library cells , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[13] Noel Menezes,et al. A “true” electrical cell model for timing, noise, and power grid verification , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[14] A. R. Newton,et al. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .
[15] Jan M. Rabaey,et al. Digital Integrated Circuits , 2003 .