Future Challenges: Defects in GaN Power Devices due to Fabrication Processes

Defects introduced through fabrication processes of GaN power devices are discussed. The dislocations threading through a freestanding GaN substrate and the upper p-n junction can act as a pathway of current leakage but the number of ‘killer’ dislocations causing significant leakage under a reverse bias is limited. Thus, the electrical property of each dislocation type needs to be studied to the exclusion of factors such as an electric field crowding and growth pits. The carrier compensation due to carbon makes it difficult to control the effective donor concentrations in n-type drift layers of high-voltage devices, so that the growth condition and method are tuned to suppress the carbon incorporation. A formation process of gate oxide produces interface states and traps in the oxide, which can be reduced by a post-deposition annealing. Ion implantation technologies for selective area doping introduce point defects which are transformed into various types of defects through post-implantation annealing, resulting in compensating holes and forming electrically inactive dopants. Ultra-high-pressure annealing at high temperature allows reducing such defects and activating dopants efficiently. To evaluate defects induced via dry etching is challenging because such defects is located near the surface. Methods to characterize etching-induced deep levels are introduced.