Miniaturization Limits for Mos Technology

The progress in miniaturization of MOSFET devices and integrated circuits has continued steadily. Even while development work using 1μm dimensions is building up, exploratory efforts in submicron devices has begun. Government funding has served to stimulate this effort, a notable step in this direction being the VHSIC program which aims to establish feasibility of 1/2μm MOSFET technology in the next few years.1 In this context the subject of limits to miniaturization has more than remote academic interest; indeed, reducing dimensions further by only a factor of two will require dealing with severe technical barriers which eventually will limit the size of MOSFET devices. None of these barriers is precisely and sharply defined, so that many design trade offs and compromises remain to be made before the ultimate dimensional limit will be known.