A low-power system-on-chip for the documentation of road accidents

The design flow and implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation, on a programmable architecture, of a compression algorithm capable of encoding up to 15 black & white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The system has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25 /spl mu/m, 6-metal standard-cell CMOS technology and works at 40 MHz, 2.5 V power supply. The adoption of IP reusable cores has allowed the system to be completed in 1 man-year time from idea to physical implementation.

[1]  Mircea R. Stan,et al.  Low-power encodings for global communication in CMOS VLSI , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Roberto Guerrieri,et al.  A 1 V, 25 /spl mu/W speech recognizer for portable systems , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[3]  염흥렬,et al.  [서평]「Applied Cryptography」 , 1997 .

[4]  Didier Le Gall,et al.  MPEG: a video compression standard for multimedia applications , 1991, CACM.

[5]  E. Filippi,et al.  The virtual chip set: a parametric IP library for system-on-a-chip design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[6]  A. Kurosawa,et al.  Integration architecture for system-on-a-chip design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).