26.6 A programmable receiver front-end achieving >17dBm IIP3 at <1.25×BW frequency offset
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[1] Sudhakar Pamarti,et al. A sharp programmable passive filter based on filtering by Aliasing , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).
[2] Ahmad Mirzaei,et al. A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications , 2012, IEEE Journal of Solid-State Circuits.
[3] Milad Darvishi,et al. A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[4] Hossein Hashemi,et al. 19.3 Reconfigurable SDR receiver with enhanced front-end frequency selectivity suitable for intra-band and inter-band carrier aggregation , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.
[5] Robert Bogdan Staszewski,et al. 3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[6] Babak Daneshrad,et al. Filtering by Aliasing , 2013, IEEE Transactions on Signal Processing.