New fault models and efficient BIST algorithms for dual-port memories

The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(/spl radic/n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF).

[1]  Kewal K. Saluja,et al.  A Novel Approach for Testing Memories Using a Built-In Self Testing Technique , 1986, International Test Conference.

[2]  Younggap You,et al.  A Self-Testing Dynamic RAM Chip , 1985, IEEE Journal of Solid-State Circuits.

[3]  Ad J. van de Goor,et al.  An overview of deterministic functional RAM chip testing , 1990, CSUR.

[4]  O. Kebichi,et al.  A new class of fault models and test algorithms for dual-port dynamic RAM testing , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.

[5]  Benoit Nadeau-Dostie,et al.  Serial interfacing for embedded-memory testing , 1990, IEEE Design & Test of Computers.

[6]  C. Rosenfeld,et al.  CAMAC staggered memory look-up module and ECL fan-in for fast trigger applications , 1991, Conference Record of the 1991 IEEE Nuclear Science Symposium and Medical Imaging Conference.

[7]  Husni Al-Muhtaseb,et al.  Efficient O(/spl radic/n) BIST algorithms for DDNPS faults in dual port memories , 1994, Proceedings., International Test Conference.

[8]  Bernard Courtois,et al.  Built-in self-test in multi-port RAMs , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[9]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[10]  Kozo Kinoshita,et al.  Test Pattern Generation for API Faults in RAM , 1985, IEEE Transactions on Computers.

[11]  X. Luo.  Performance evaluation of a multiprocessor system with dual-port directory caches , 1991, [1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings.

[12]  Manuel J. Raposa.  Dual port static RAM testing , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[13]  Peter Muhmenthaler,et al.  Enhanced fault modeling for DRAM test and analysis , 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

[14]  Kewal K. Saluja,et al.  Built-in self-testing of random-access memories , 1990, Computer.

[15]  Hideto Hidaka,et al.  A high-density dual-port memory cell operation and array architecture for ULSI DRAMs , 1992 .

[16]  Michael Nicolaidis,et al.  Testing complex couplings in multiport memories , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Michael Nicolaidis,et al.  Theory of Transparent BIST for RAMs , 1996, IEEE Trans. Computers.

[18]  A. Tuszynski.  Self-learning machines applied to the testing of semiconductor memories , 1978 .

[19]  Janak H. Patel,et al.  Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories , 1989, IEEE Trans. Computers.

[20]  T. G. Clarkson,et al.  A modular based parallel image processing system , 1990, Proceedings of the 33rd Midwest Symposium on Circuits and Systems.

[21]  KOZO KINOSHITA,et al.  Built-In Testing of Memory Using an On-Chip Compact Testing Scheme , 1984, IEEE Transactions on Computers.

[22]  Imtiaz Ahmad,et al.  Post-processor for data path synthesis using multiport memories , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[23]  Hugo De Man,et al.  Testability strategy and test pattern generation for register files and customized memories , 1990, Microprocess. Microsystems.

[24]  J. C. Smith.  The SARAM (sequential access and random access memory), a new kind of dual-port memory for communications now and beyond , 1993, Proceedings of WESCON '93.

[25]  Shuichi Kato,et al.  A flexible multiport RAM compiler for data path , 1991 .

[26]  Kewal K. Saluja,et al.  Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  A. Gibbons.  Algorithmic Graph Theory , 1985 .

[28]  Steve McGeady.  The i960CA SuperScalar implementation of the 80960 architecture , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.

[29]  G. M. Lattimore,et al.  A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test , 1992 .

[30]  M. Sekiya,et al.  A field memory system for home-video editing , 1989 .