FPGA Implementation of the Conjugate Gradient Method

The rational fraction number system is proposed to solve the algebraic problems in FPGA devices. The fraction number consists of the n-bit integer numerator and the n -bit integer denominator, and can represent numbers with 2n bit mantissa. Experimental linear equation system solver was developed in FPGA device, which implements the recursive conjugate gradient method. Its hardware arithmetic unit can calculate addition, multiplication, and division of fraction numbers with n=35 in a pipelined mode. The proposed unit operates with the band matrices with the dimensions up to 3500.

[1]  W. Neville Holmes.  Composite Arithmetic: Proposal for a New Standard , 1997, Computer.

[2]  Oleg Maslennikov,et al.  Configurable Microprocessor Array for DSP Applications , 2003, PPAM.

[3]  Yong Dou,et al.  64-bit floating-point FPGA matrix multiplication , 2005, FPGA '05.

[4]  Karl S. Hemmert,et al.  Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[5]  Mary Jane Irwin,et al.  A rational arithmetic processor , 1981, 1981 IEEE 5th Symposium on Computer Arithmetic (ARITH).

[6]  Gene H. Golub,et al.  Matrix computations , 1983 .

[7]  Oleg Maslennikov,et al.  Implementation of Givens QR-Decomposition in FPGA , 2001, PPAM.