Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device

Reconfigurable logic devices are usually classified on the basis of their basic logic cell architecture as fine-grained or coarse-grained. In general, each architecture is suitable on its own merit; therefore, it is difficult to achieve a balance between the operation speed and area-efficiency in applications. In order to solve this problem, we propose a new logic cell architecture based on a 4-bit ripple carry adder that includes configuration memory bits. This is called the variable grain logic cell architecture, VGLC. It is possible to realize two features by using the VGLC: one is a high device speed of a coarse-grained cell and the other is the versatile logic of a fine-grained cell. This paper demonstrates the transistor-level optimization of our proposed logic cell. Moreover, based on the results of the evaluation, the authors show that the critical path delay can be reduced by a maximum of 37% when using the proposed logic cell architecture is used in a 32-bit multiplier