Code Decompression Unit Design for VLIW Embedded Processors

Code size "bloating" in embedded very long instruction word (VLIW) processors is a major concern for embedded systems since memory is one of the most restricted resources. In this paper, we describe a code compression algorithm based on arithmetic coding, discuss how to design decompression architecture, and illustrate the tradeoffs between compression ratio and decompression overhead, by using different probability models. Experimental results for a VLIW embedded processor TMS320C6x show that compression ratios between 67% and 80% can be achieved, depending on the probability models used. A precache decompression unit design is implemented in TSMC 0.25 mum and a test chip is fabricated.

[1]  Junqiang Sun,et al.  Tms320c6000 cpu and instruction set reference guide , 2000 .

[2]  Wayne H. Wolf,et al.  SAMC: a code compression algorithm for embedded processors , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Giovanni Squillero,et al.  On the test of microprocessor IP cores , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[4]  Andrew Wolfe,et al.  Executing compressed programs on an embedded RISC architecture , 1992, MICRO 1992.

[5]  Jacob A. Abraham,et al.  Reuse of addressable system bus for SOC testing , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[6]  Dimitris Gizopoulos,et al.  Software-based self-testing of embedded processors , 2005, IEEE Transactions on Computers.

[7]  Hideo Fujiwara,et al.  Instruction-Based Self-Testing of Delay Faults in Pipelined Processors , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Jeffrey Scott Vitter,et al.  Parallel Lossless Image Compression Using Huffman and Arithmetic Coding , 1996, Inf. Process. Lett..

[9]  Paolo Faraboschi,et al.  Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools , 2004 .

[10]  Jacob A. Abraham,et al.  Native mode functional self-test generation for Systems-on-Chip , 2002, Proceedings International Symposium on Quality Electronic Design.

[11]  Kwang-Ting Cheng,et al.  A self-test methodology for IP cores in bus-based programmable SoCs , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[12]  Kwang-Ting Cheng,et al.  On a software-based self-test methodology and its application , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[13]  Sujit Dey,et al.  A scalable software-based self-test methodology for programmable processors , 2003, DAC '03.

[14]  Kwang-Ting Cheng,et al.  Instruction-level DfT for testing processor and IP cores in system-on-a-chip , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[15]  Abraham Lempel,et al.  A universal algorithm for sequential data compression , 1977, IEEE Trans. Inf. Theory.

[16]  A. Wolfe,et al.  Executing Compressed Programs On An Embedded RISC Architecture , 1992, [1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25.

[17]  Yuan Xie,et al.  Code Compression for VLIW Processors , 2001, Data Compression Conference.

[18]  Robert K. Montoye,et al.  A decompression core for PowerPC , 1998, IBM J. Res. Dev..

[19]  Jacob A. Abraham,et al.  Automated mapping of pre-computed module-level test sequences to processor instructions , 2005, IEEE International Conference on Test, 2005..