Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations

[1]  Yu Kou,et al.  On circulant low density parity check codes , 2002, Proceedings IEEE International Symposium on Information Theory,.

[2]  Keshab K. Parhi,et al.  A 54 Mbps (3,6)-regular FPGA LDPC decoder , 2002, IEEE Workshop on Signal Processing Systems.

[3]  Yanni Chen,et al.  A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[4]  Joseph R. Cavallaro,et al.  Semi-parallel reconfigurable architectures for real-time LDPC decoding , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[5]  Shu Lin,et al.  Near-Shannon-limit quasi-cyclic low-density parity-check codes , 2004, IEEE Trans. Commun..

[6]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[7]  Zongwang Li,et al.  A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[8]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[9]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[10]  A. J. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[11]  In-Cheol Park,et al.  Memory-based low density parity check code decoder architecture using loosely coupled two data-flows , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[12]  Nozomu Togawa,et al.  Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm , 2005, 2005 International Conference on Computer Design.

[13]  Keshab K. Parhi,et al.  VLSI implementation issues of TURBO decoder design for wireless applications , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[14]  Zhongfeng Wang,et al.  A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[15]  Keshab K. Parhi,et al.  Area efficient decoding of quasi-cyclic low density parity check codes , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[16]  Gwan S. Choi,et al.  FPGA based implementation of decoder for array low-density parity-check codes , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

[17]  Zongwang Li,et al.  Efficient encoding of quasi-cyclic low-density parity-check codes , 2006, IEEE Trans. Commun..

[18]  A. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[19]  Shu Lin,et al.  Near Shannon limit quasi-cyclic low-density parity-check codes , 2004, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).

[20]  Rüdiger L. Urbanke,et al.  Efficient encoding of low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.

[21]  K.K. Parhi,et al.  Efficient high-speed quasicyclic LDPC decoder architecture , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..

[22]  Tong Zhang,et al.  On finite precision implementation of low density parity check codes decoder , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[23]  Jaekyun Moon,et al.  Parallel VLSI architectures for a class of LDPC codes , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[24]  Jinghu Chen,et al.  Near optimum universal belief propagation based decoding of low-density parity check codes , 2002, IEEE Trans. Commun..

[25]  Zhongfeng Wang,et al.  Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[26]  Frank Kienle,et al.  A synthesizable IP core for DVB-S2 LDPC code decoding , 2005, Design, Automation and Test in Europe.

[27]  Dale E. Hocevar.  LDPC code construction with flexible hardware implementation , 2003, IEEE International Conference on Communications, 2003. ICC '03..

[28]  Wayne Luk,et al.  A flexible hardware encoder for low-density parity-check codes , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[29]  B. Nikolic,et al.  Architectures and implementations of low-density parity check decoding algorithms , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[30]  Marc P. C. Fossorier,et al.  Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Matrices , 2004, IEEE Trans. Inf. Theory.