Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs

Switching speed, active power consumption, standby leakage current, and silicon area are major concerns in buffer design. A new Skewed-IO cell with two split inputs and two split outputs is proposed for low-leakage and high-speed buffer design in this paper. The triple-threshold-voltage buffers with the new Skewed-IO cells offer up to 68.3% and 13.2% reduction in standby leakage currents and propagation delay, respectively, as compared to the conventional static CMOS inverter based buffers under identical load capacitance conditions in a TSMC 65 nm CMOS technology.

[1]  Massimo Alioto,et al.  Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[2]  Hua Wang,et al.  Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Zhiyu Liu,et al.  Leakage-Aware Design of Nanometer SoC , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[4]  Ying Zhang,et al.  A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management , 2010, IEEE Journal of Solid-State Circuits.

[5]  Eby G. Friedman,et al.  Multi-voltage CMOS Circuit Design , 2006 .

[6]  Yehea I. Ismail,et al.  Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Eby G. Friedman,et al.  Unification of speed, power, area, and reliability in CMOS tapered buffer design , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[8]  Eby G. Friedman,et al.  Multi-Voltage CMOS Circuit Design: Kursun/Multi-Voltage CMOS Circuit Design , 2006 .

[9]  Sung-Mo Kang,et al.  CMOS digital integrated circuits , 1995 .

[10]  Resve Saleh,et al.  Analysis and Design of Digital Integrated Circuits , 1983 .

[11]  Volkan Kursun,et al.  Application-specific selection of 6T SRAM cells offering superior performance and quality with a triple-threshold-voltage CMOS technology , 2011, 2011 3rd Asia Symposium on Quality Electronic Design (ASQED).