Hardware implementation of 3D pipelined laplace filter based on rotation structures

A hardware implementation of 3D pipelined Laplace filter has been presented in the paper. The filter is composed of rotation and delay unit structures with a help of CORDIC algorithm. Synthesis of the pipelined 3D Laplace filter is based on synthesis of 2D and ID filters. Proposed implementation of the filter has been compared to the implementation of the filter based on direct form. Parameters of both filter structures implemented in FPGA, have been measured and compared.

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